PULP Community

Threads

1. problem when generating boot rom using boot_code.sv (5 Replies)
2. Error When Running hwme example (3 Replies)
3. RI5CY - FPGA Synthesis (0 Replies)
4. Error when building Pulpissimo (2 Replies)
5. error when using DC to synthesis pulpino (1 Reply)
6. [HWPE] Microcode (4 Replies)
7. match problem between Python3 and pip3 (1 Reply)
8. FPGA JTAG-cable and debugger sw (5 Replies)
9. How to build SDK for PULPino? (0 Replies)
10. pulp-soc-defines.sv (0 Replies)
11. problem when testing gcc (2 Replies)
12. Errors encountered when compiling the toolchain (2 Replies)
13. RISC-V GNU Compiler Toolchain: Build Error (4 Replies)
14. What do I need to do before a taping out of PULPino? (5 Replies)
15. OpenMP example for PULP not working (7 Replies)
16. Pulpissimo on FPGA (1 Reply)
17. Coremark for benchmarking 8 core PULP (2 Replies)
18. UVM testbench for PULPINO (3 Replies)
19. Post-synthesis simulation for pulp (1 Reply)
20. Synthesis 8 core pulp for ASIC (3 Replies)