(12-01-2020, 08:05 PM)igor.lima Wrote: Hi!

I'm new in community, i'd like some help!

I'm trying to run the Hello example from "https://github.com/pulp-platform/pulp-rt-examples" in my Nexys Video FPGA using the bitstream of Pulpissimo.

Until now i'm just following the instructions from README.md file from "https://github.com/pulp-platform/pulpissimo".

I had download and install the Toolchain from pulp-riscv-gnu-toolchain as "Newlib", could someone confirm that it is not necessary install the "Linux" version of this toolchain?


Then i installed the Standard Pulp SDK from "https://github.com/pulp-platform/pulp-sdk/#standard-sdk-build"

I had some issues following the steps, most of them are related with missing steps, like configuring bashrc or some ambient variable, but i was able to solve all of them i believe. I miss some kind of step-by-step, from rtl to running example on FPGA, is it possible create something like that? I think it could be done as a new Thread in forum for the communty, it could help a lot.

I was able to generate the bitstream of Pulpissimo and configure it in Nexys Video FPGA using the JTAG-USB connection. When i run the specific OpenOCD from Pulp-SDK, the OpenOCD is able to identify the Pulpissimo processor in FPGA.

Then i compiled the Hello Example after adding the two weakly defined variables as suggested to configure core and peripherics frequencies. It was compiled with success, the ELF file was properly generate in the build directory.

My problem happen when i had try to use GDB with ELF file to load it to L2 memory of Pulpissimo, the connection between the GDB and OpenOCD looks fine, when i use the Load command it copy the elf file to memory it looks to work fine too, but when i use the Continue command it stops and never end the execution, but it print some kind of assembly commands like;
# j    1c0080ec <__rt_illegal_instr>

So i did the check with gcc in the ELF file to check the Assembly, as suspected it was printing the assembly that has some kind of error i believe, the first piece of assembly code is like that;

Code:

test:     file format elf32-littleriscv


Disassembly of section .vectors:

1c008000 <__irq_vector_base>:
1c008000:    0ec0006f              j    1c0080ec <__rt_illegal_instr>
1c008004:    0900006f              j    1c008094 <__rt_no_irq_handler>
1c008008:    08c0006f              j    1c008094 <__rt_no_irq_handler>
1c00800c:    0880006f              j    1c008094 <__rt_no_irq_handler>
1c008010:    0840006f              j    1c008094 <__rt_no_irq_handler>
1c008014:    0800006f              j    1c008094 <__rt_no_irq_handler>
1c008018:    07c0006f              j    1c008094 <__rt_no_irq_handler>
1c00801c:    0780006f              j    1c008094 <__rt_no_irq_handler>
1c008020:    0740006f              j    1c008094 <__rt_no_irq_handler>
1c008024:    0700006f              j    1c008094 <__rt_no_irq_handler>
1c008028:    06c0006f              j    1c008094 <__rt_no_irq_handler>
1c00802c:    0680006f              j    1c008094 <__rt_no_irq_handler>
1c008030:    0640006f              j    1c008094 <__rt_no_irq_handler>
1c008034:    0600006f              j    1c008094 <__rt_no_irq_handler>
1c008038:    05c0006f              j    1c008094 <__rt_no_irq_handler>
1c00803c:    0580006f              j    1c008094 <__rt_no_irq_handler>
1c008040:    0540006f              j    1c008094 <__rt_no_irq_handler>
1c008044:    0500006f              j    1c008094 <__rt_no_irq_handler>
1c008048:    04c0006f              j    1c008094 <__rt_no_irq_handler>
1c00804c:    0480006f              j    1c008094 <__rt_no_irq_handler>
1c008050:    0440006f              j    1c008094 <__rt_no_irq_handler>
1c008054:    0400006f              j    1c008094 <__rt_no_irq_handler>
1c008058:    03c0006f              j    1c008094 <__rt_no_irq_handler>
1c00805c:    0380006f              j    1c008094 <__rt_no_irq_handler>
1c008060:    0340006f              j    1c008094 <__rt_no_irq_handler>
1c008064:    0300006f              j    1c008094 <__rt_no_irq_handler>
1c008068:    02c0006f              j    1c008094 <__rt_no_irq_handler>
1c00806c:    0280006f              j    1c008094 <__rt_no_irq_handler>
1c008070:    0240006f              j    1c008094 <__rt_no_irq_handler>
1c008074:    0200006f              j    1c008094 <__rt_no_irq_handler>
1c008078:    01c0006f              j    1c008094 <__rt_no_irq_handler>
1c00807c:    0180006f              j    1c008094 <__rt_no_irq_handler>

1c008080 <_start>:
1c008080:    0200006f              j    1c0080a0 <_entry>
1c008084:    0680006f              j    1c0080ec <__rt_illegal_instr>
    ...

1c008090 <__rt_debug_struct_ptr>:
1c008090:    0cf4                    addi    a3,sp,604
1c008092:    1c00                    addi    s0,sp,560

1c008094 <__rt_no_irq_handler>:
1c008094:    0000006f              j    1c008094 <__rt_no_irq_handler>

1c008098 <__rt_semihosting_call>:
1c008098:    00100073              ebreak
1c00809c:    00008067              ret

Disassembly of section .text:

1c0080a0 <_entry>:
1c0080a0:    7a101073              csrw    pcmr,zero
1c0080a4:    ffff9297              auipc    t0,0xffff9
1c0080a8:    d2c28293              addi    t0,t0,-724 # 1c000dd0 <_bss_start>
1c0080ac:    ffff9317              auipc    t1,0xffff9
1c0080b0:    e0030313              addi    t1,t1,-512 # 1c000eac <__l2_priv0_end>
1c0080b4:    0002a023              sw    zero,0(t0)
1c0080b8:    0291                    addi    t0,t0,4
1c0080ba:    fe62ede3              bltu    t0,t1,1c0080b4 <_entry+0x14>
1c0080be:    ffff9117              auipc    sp,0xffff9
1c0080c2:    c0210113              addi    sp,sp,-1022 # 1c000cc0 <stack>
1c0080c6:    292000ef              jal    ra,1c008358 <__rt_init>
1c0080ca:    00000513              li    a0,0
1c0080ce:    00000593              li    a1,0
1c0080d2:    00000397              auipc    t2,0x0
1c0080d6:    26438393              addi    t2,t2,612 # 1c008336 <main>
1c0080da:    000380e7              jalr    t2
1c0080de:    842a                    mv    s0,a0
1c0080e0:    350000ef              jal    ra,1c008430 <__rt_deinit>
1c0080e4:    8522                    mv    a0,s0
1c0080e6:    330010ef              jal    ra,1c009416 <exit>

1c0080ea <_fini>:
1c0080ea:    8082                    ret

1c0080ec <__rt_illegal_instr>:
1c0080ec:    fe112e23              sw    ra,-4(sp)
1c0080f0:    fea12c23              sw    a0,-8(sp)
1c0080f4:    00000517              auipc    a0,0x0
1c0080f8:    3ba50513              addi    a0,a0,954 # 1c0084ae <__rt_handle_illegal_instr>
1c0080fc:    010000ef              jal    ra,1c00810c <__rt_call_c_function>
1c008100:    ffc12083              lw    ra,-4(sp)
1c008104:    ff812503              lw    a0,-8(sp)
1c008108:    30200073              mret

1c00810c <__rt_call_c_function>:
1c00810c:    7119                    addi    sp,sp,-128
1c00810e:    c006                    sw    ra,0(sp)
1c008110:    c20e                    sw    gp,4(sp)
1c008112:    c412                    sw    tp,8(sp)
1c008114:    c616                    sw    t0,12(sp)

What could i have done to generate some kind of illegal instruction during the compiling process? is it not wrong after all?

When i use the gdb command "disas" it print the C code properly...

If you need any more information, just ask

Any help will be very helpful

Best Regards, Igor Ruschi

Quote:LPLA, thanks for replay!
the simulation was not executed because i already have the FPGA, there are no reason to run the simulation if i already have a tested FPGA, my problem as described is not in FPGA target, but in assembly generated by compiler, for while it doesn't matter what kind of platform i will use to run the pulpissimo, simulation or FPGA will broke anyway because the instructions are wrong, so it is just a compile issue.

Quote:export PULP_RISCV_GCC_TOOLCHAIN=/opt/riscv/

export VSIM_PATH=/home/caninos/Documents/pulpissimo/repo/pulpissimo/sim

PATH=$PATH:/opt/riscv/bin

source /home/caninos/Documents/pulpissimo/repo/pulp-sdk/init.sh
source /home/caninos/Documents/pulpissimo/repo/pulp-sdk/sourceme.sh

Quote:adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
 0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
 1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 1024 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
...

Quote:(gdb) load
Loading section .data_tiny_fc, size 0x31c lma 0x1c000004
Loading section .init_array, size 0x2c lma 0x1c000320
Loading section .fini_array, size 0xc lma 0x1c00034c
Loading section .rodata, size 0x168 lma 0x1c000358
Loading section .data, size 0x10c lma 0x1c000cc0
Loading section .vectors, size 0xa0 lma 0x1c008000
Loading section .text, size 0x1f80 lma 0x1c0080a0
Loading section .l2_data, size 0x6c lma 0x1c010000
Start address 0x1c008080, load size 9812
Transfer rate: 7 KB/sec, 1226 bytes/write.
(gdb) disas
Dump of assembler code for function _start:
=> 0x1c008080 <+0>:    j    0x1c0080a0 <_stext>
   0x1c008084 <+4>:    j    0x1c0080ec <__rt_illegal_instr>
   0x1c008088 <+8>:    unimp
   0x1c00808a <+10>:    unimp
   0x1c00808c <+12>:    unimp
   0x1c00808e <+14>:    unimp
End of assembler dump.

(12-02-2020, 10:46 AM)LPLA Wrote: Did you try running a RTL simulation first?

If that works then make sure you followed the steps on GitHub and source the right files before compiling an App for FPGA.

After loading the program to L2 you should set a breakpoint.
So basically in gdb you do:
1) load
2) b exit
3) continue

Did you have any output on minicom or screen?