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+--- Thread: Question about bitstream generation (/showthread.php?tid=236)
Question about bitstream generation - zorrolee777 - 02-04-2021
Hi, I'm new to this and got some errors when generating the bitstream file.
The code I ran:
Code:
$ cd $COREVMCU/fpga
$ make clean_nexys rev=nexysA7-100T
$ make nexys rev=nexysA7-100TCode:
ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:48]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_slow_clk_gen' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:24]
ERROR: [Synth 8-6156] failed synthesizing module 'safe_domain' [/home/core-v-mcu/rtl/pulpissimo/safe_domain.sv:12]
ERROR: [Synth 8-6156] failed synthesizing module 'pulpissimo' [/home/core-v-mcu/rtl/pulpissimo/pulpissimo.sv:13]
ERROR: [Synth 8-6156] failed synthesizing module 'xilinx_pulpissimo' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v:22]When I commented out the module, some other errors would come out, saying those modules are not found. I guess there're four of them, which are xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. I'm not sure if those modules are supposed to be generated by myself, or where should I get and put them? Any comments would be appreciated. Thanks in advance!
Sincerely,
Zorro
RE: Question about bitstream generation - meggiman - 02-11-2021
Hi Zorro,
First of all, which project are you actually trying to generate a bitstream for? PULPissimo? PULP-open? If it is PULPissimo: Are there any other errors further up the command log? The make target is supposed to first generate these Xilinx IPs as individual projects for you before invoking the main FPGA target. All of these IPs have a dedicated make file to generate them in fpga/pulpissimo-nexys/ips (although they should be called automatically with the main 'nexys' target).
Best,
Manuel
RE: Question about bitstream generation - zorrolee777 - 02-16-2021
(02-11-2021, 12:41 PM)meggiman Wrote: Hi Zorro,
First of all, which project are you actually trying to generate a bitstream for? PULPissimo? PULP-open? If it is PULPissimo: Are there any other errors further up the command log? The make target is supposed to first generate these Xilinx IPs as individual projects for you before invoking the main FPGA target. All of these IPs have a dedicated make file to generate them in fpga/pulpissimo-nexys/ips (although they should be called automatically with the main 'nexys' target).
Best,
Manuel
Hello Manuel,
Thank you so much for your reply! I'm using PULPissimo, and didn't get any errors before this step. I check the path you mentioned and I did find the IPs there. Then I tried to run the makefile in the /fpga/pulpissimo-nexys/ips/xilinx_clk_mngr manually, but got this error massage:
Setting environment variables for nexys board
make: *** No rule to make target 'nexys'. Stop.
Does this mean there are some problems when setting up these Xilinx IPs? If so how should I solve this?
Thanks,
Zorro
RE: Question about bitstream generation - meggiman - 02-23-2021
You should call the appropriate make target (check the Makefile in the ips/xilinx_clk_mngr). There is no nexys target there. Use 'make all'.
RE: Question about bitstream generation - zorrolee777 - 02-23-2021
(02-23-2021, 02:24 PM)meggiman Wrote: You should call the appropriate make target (check the Makefile in the ips/xilinx_clk_mngr). There is no nexys target there. Use 'make all'.
Thanks for your reply! When I run 'make all' I would receive the following errors:
/pulpissimo-nexys/ips/xilinx_clk_mngr $ make all
../../fpga-settings.mk:33: ***
No Nexys board revision given. Please use 'make nexys rev=[nexys4|nexys4DDR|nexysA7-100T|nexysA7-50T]'
. Stop.
That's why I target nexys. Any suggestions would be appreciated. Thanks.