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+--- Thread: How to clock gate the Pulpino (/showthread.php?tid=277)
How to clock gate the Pulpino - CongHuang - 12-28-2021
Hello, team!
I am currently working on a project related to PULPino. I am wondering how to put the core in the IDLE state. The datasheet introduces an apb_event_unit for clock gating everything else and waking up the core if an event/interrupt arrives. I notice there is another peripheral, apb_pulpino contains CLK Gate as well.
However, while running benchmarks such as hello/fft/sha/fir, I could not find the situations when the core is in the IDLE state. In other words, the clock signal is not gated during the entire operation. Is the clock gating function being enabled? Is there any benchmark I can use to test the clock gating (it would be better if the riscv-core and peripherals can be clock gated simultaneously)?
Thanks for your kind reply！
RE: How to clock gate the Pulpino - kgf - 12-28-2021
PULPino is a very simple system, where all work is done by the processor. If you halt the processor core, your program will also not execute, so benchmarks like fir will not have the core halting. What you refer to is usually done when the processor needs to go to sleep, so it will make the proper setup (for either a timer or the environment) and execute a wait for interrupt (wfi) to go to sleep until this interrupt comes. There should be some examples for that, but I do not know the exact path
See a bit of the discussion on:
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/sleep.html
For the sleep mode. More complex systems (PULPissimo or PULPopen which has an additional cluster with several RISC-V cores for example) will have units that can continue to work while one or more RISC-V cores are put to sleep.
Note that finer grain clock gating can be/is being used for components that support it. I.e. if you do not have FP operations the FPU will/could be clock gated.
Cheers,
KGF