PULP Community
Synthesis with Intel FPGA Quartus - Printable Version

+- PULP Community (https://pulp-platform.org/community)
+-- Forum: PULP's Community forum (https://pulp-platform.org/community/forumdisplay.php?fid=1)
+--- Forum: PULP General questions (https://pulp-platform.org/community/forumdisplay.php?fid=2)
+--- Thread: Synthesis with Intel FPGA Quartus (/showthread.php?tid=291)



Synthesis with Intel FPGA Quartus - david.castells - 06-06-2022

Did anybody check that the PULP platform (in general, I mean several projects) SystemVerilog compiles with Intel FPGA Quartus toolchain ?

I tried with cvfpu and did not work for me. Maybe I missed something, but I had the impression that you are using some SystemVerilog features not supported by Quartus Prime (v. 21.1).


RE: Synthesis with Intel FPGA Quartus - kgf - 06-06-2022

Can you maybe elaborate? Altera devices are not frequently targeted by us (there is nothing wrong with them, we just ended up using more Xilinx boards for historical reasons), so we might have missed something. But of you can open an issue on GitHub someone might be able to fix it easily. 

Cheers,
KGF