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+--- Thread: PULP CORE TAPE OUT (/showthread.php?tid=298)
PULP CORE TAPE OUT - giumaug - 09-29-2022
Hi,
looking at website, I see several cores have been taped out.
I'm trying to find more info in how tape out has been carried out.
Is the tape out flow fully based on the RTL of the cores (the one available on GitHub repos) or human circuit customization has been
performed ?
For example, looking at https://github.com/openhwgroup/cv32e40p core I see the register file is described at high level as a simple array.
When it comes to circuit implementation has the synthesis had free room to decide how to translate the RF in real digital circuit or some human
customization has been carried out?
RE: PULP CORE TAPE OUT - kgf - 09-29-2022
The tape-outs are using the repos on GitHub. However, every design needs technology specific 'adjustments', for example the I/O cells, and memory macros will have different names/connections for every target technology. Also most RTL code has several different parameters that allows it to be customized (is the register file FF or latch based?) to different needs and constraints. So there will be a customized 'instance' that will be used for the tape-out. Various NDAs prevent us from making these public at the moment.
We aim to have everything published (as long as we are legally able to), some work that is still in development is in internal repos, but once we push our repositories to GitHub we rely on these repos for our work as well. Anything that is on GitHub is what we use for the chips as well.
For the register file.. it is implemented as a simple array..