Synthesis of ARA Vector Unit - Printable Version +- PULP Community (https://pulp-platform.org/community) +-- Forum: PULP's Community forum (https://pulp-platform.org/community/forumdisplay.php?fid=1) +--- Forum: PULP General questions (https://pulp-platform.org/community/forumdisplay.php?fid=2) +--- Thread: Synthesis of ARA Vector Unit (/showthread.php?tid=352) |
Synthesis of ARA Vector Unit - Tanishq S - 08-07-2024 Respected Moderator I am currently working on synthesizing the ARA architecture along with the CVA6 processor. I have been trying to perform top-down mapping of the files by designating ara_soc.sv as the top module and consolidating all related files into a single .sv file for synthesis. Unfortunately, I have encountered difficulties in achieving a successful synthesis in Cadence Genus. I am concerned that my approach might be flawed, and I am seeking guidance on how to resolve this issue. Could you please provide me with some advice or best practices for synthesizing the ARA and CVA6 design in Cadence Genus or any other tool like Vivado or Synopsis DC? Any insights or suggestions on how to effectively manage the integration of these components would be greatly appreciated. RE: Synthesis of ARA Vector Unit - kgf - 08-12-2024 Hello, There is nothing particularly different from any other project. What exactly is "encountered difficulties in achieving a successful synthesis", is this quality of results, warnings, errors? Technically speaking you DO NOT need to consolidate files. Any modern synthesizer should be able to read in a file list. We use bender: https://github.com/pulp-platform/bender To help us in generating the scripts, file lists. But it is not strictly needed. Cheers, KGF RE: Synthesis of ARA Vector Unit - Tanishq S - 08-12-2024 (08-12-2024, 08:50 AM)kgf Wrote: Hello, Respected Moderator 1. I tried to generate the scripts for Genus Synthesis using the method mentioned in previous mail and i got this tcl file : attached in "run_tcl.txt" [little modified] run_tcl.txt (Size: 25.53 KB / Downloads: 1) 2. Then after running this run.tcl in Cadence Genus i got this log file : attached in "log.txt" log.txt (Size: 56.6 KB / Downloads: 1) For this execution i am running Synthesis without any Constraints given. Given the nature of the errors, I am concerned that this approach might lead to a series of issues as we proceed. While I could troubleshoot these errors step by step, I believe it might be more efficient to use the same synthesis tool utilized mentioned in paper—Synopsys Design Compiler (DC). Could you please provide me with the correct procedure for synthesis using Genus without encountering any error while , if possible? Additionally, if you think switching to Synopsys DC would be more effective, I would appreciate your guidance on that as well. Thank you in advance for your assistance. I look forward to your advice on the best course of action to achieve a successful synthesis. |