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+--- Thread: update to ri5cy core interrupt system and toolchain (/showthread.php?tid=57)
update to ri5cy core interrupt system and toolchain - lightning_fingers - 12-27-2018
Hello!
I am investigating using the ri5cy core for a commercial application.
Quite some time ago I looked into the ri5cy core via the Embecosm githubu fork:
https://github.com/embecosm/ri5cy
This seems to (now) be a quite old version of the core (32 interrupt inputs, much different csr implementation).
So, I've updated my core payload with the latest ri5cy rtl build.
I now have problems with my prototype interrupt code.
In C I have:
in "main()" {
set_csr (0x300, 0x00000009); //enable interrupts?
write_csr(0x305, my_isr); // isr address?
// big long delay
for (int i=0;i<10000;i++) asm("NOP");
}
void __attribute__ ((interrupt())) my_isr (){
*simresult = (unsigned short int) 0xF111; // flag result
}
which gives me:
00000300 <my_isr>:
300: ff010113 addi sp,sp,-16
304: 00f12423 sw a5,8(sp)
308: 00e12623 sw a4,12(sp)
30c: 40002703 lw a4,1024(zero) # 400 <simresult>
310: 0000f7b7 lui a5,0xf
314: 11178793 addi a5,a5,273 # f111 <_end+0xece5>
318: 00f72023 sw a5,0(a4)
31c: 00c12703 lw a4,12(sp)
320: 00812783 lw a5,8(sp)
324: 01010113 addi sp,sp,16
328: 10000073 eret
The compiler is inserting the correct isr handling code......
But when simulated with the latest ri5cy core I get:
# - DGB - write 0 into CTRL
# 2465870000 ps: Illegal instruction (core 0) at PC 0x00000328:
# 2469762000 ps: Illegal instruction (core 0) at PC 0x00000328:
I read in the riscv documentation that eret should now probably be an mret.
(At present I am using the embecosm modified toolchain (gcc).)
where can I download the "official" build gcc build tools for the latest ri5cy core (including all of the ri5cy additions like the hardware loop functionality)?
Many thanks in advance
RE: update to ri5cy core interrupt system and toolchain - lightning_fingers - 12-28-2018
(12-27-2018, 09:25 AM)lightning_fingers Wrote: in "main()" {
set_csr (0x300, 0x00000009); //enable interrupts?
write_csr(0x305, my_isr); // isr address?
// big long delay
for (int i=0;i<10000;i++) asm("NOP");
}
void __attribute__ ((interrupt())) my_isr (){
*simresult = (unsigned short int) 0xF111; // flag result
}
which gives me:
00000300 <my_isr>:
300: ff010113 addi sp,sp,-16
304: 00f12423 sw a5,8(sp)
308: 00e12623 sw a4,12(sp)
30c: 40002703 lw a4,1024(zero) # 400 <simresult>
310: 0000f7b7 lui a5,0xf
314: 11178793 addi a5,a5,273 # f111 <_end+0xece5>
318: 00f72023 sw a5,0(a4)
31c: 00c12703 lw a4,12(sp)
320: 00812783 lw a5,8(sp)
324: 01010113 addi sp,sp,16
328: 10000073 eret
The compiler is inserting the correct isr handling code......
But when simulated with the latest ri5cy core I get:
# - DGB - write 0 into CTRL
# 2465870000 ps: Illegal instruction (core 0) at PC 0x00000328:
# 2469762000 ps: Illegal instruction (core 0) at PC 0x00000328:
I've managed work around this version of the tool chain I am using by hacking the memory image that I read into my memory models in my RTL stimulus env.
i.e. replace any opcodes eret (32'h10000073) with mret (32'h30200073)
this is obviously a very short term fix, but does at least allow me to continue this particular RTL simulation.
With this hack, the simulation executes as expected.
RE: update to ri5cy core interrupt system and toolchain - lightning_fingers - 01-03-2019
anyone?
where can I download/build the latest software tools for the latest RI5CY core?
thanks
RE: update to ri5cy core interrupt system and toolchain - lightning_fingers - 01-04-2019
(01-03-2019, 11:05 AM)lightning_fingers Wrote: anyone?
where can I download/build the latest software tools for the latest RI5CY core?
thanks
I've been in contact via twitter, and got a reply, suggesting:
https://github.com/pulp-platform/pulp-riscv-gnu-toolchain
yet when I build this toolchain, I cant use the -march=IMXpulpv2 switch when trying to compile some c code, like:
riscv32-unknown-elf-gcc -nostdlib -nostartfiles -Tlink.ld -O3 -march=IMXpulpv2 -o hello.o hello.c
I get:
Fatal error: -march=IMXpulpv2: ISA string must begin with rv32 or rv64
I built the tool chain with:
./configure --with-arch=rv32imc --with-cmodel=medlow --enable-multilib
anyone have any ideas how I can build the latest ri5cy toolchain then compile some c code which will use the latest ri5cy hardware additions/extensions?
note: the pulp-platform tools emit perfectly fine riscv 32 bit code, I need to know how to generate ri5cy code.
many thanks
RE: update to ri5cy core interrupt system and toolchain - lightning_fingers - 01-04-2019
(01-04-2019, 07:26 AM)lightning_fingers Wrote:(01-03-2019, 11:05 AM)lightning_fingers Wrote: anyone?
where can I download/build the latest software tools for the latest RI5CY core?
thanks
I've been in contact via twitter, and got a reply, suggesting:
https://github.com/pulp-platform/pulp-riscv-gnu-toolchain
yet when I build this toolchain, I cant use the -march=IMXpulpv2 switch when trying to compile some c code, like:
riscv32-unknown-elf-gcc -nostdlib -nostartfiles -Tlink.ld -O3 -march=IMXpulpv2 -o hello.o hello.c
I get:
Fatal error: -march=IMXpulpv2: ISA string must begin with rv32 or rv64
I built the tool chain with:
./configure --with-arch=rv32imc --with-cmodel=medlow --enable-multilib
anyone have any ideas how I can build the latest ri5cy toolchain then compile some c code which will use the latest ri5cy hardware additions/extensions?
note: the pulp-platform tools emit perfectly fine riscv 32 bit code, I need to know how to generate ri5cy code.
many thanks
through trial and error I found the arch string required is march=rv32imxpulpv3
this then generates code I can see uses the hardware loop extensions.