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+--- Thread: FPGA JTAG-cable and debugger sw (/showthread.php?tid=72)
FPGA JTAG-cable and debugger sw - Akim - 03-28-2019
Hello,
We have bought couple of Genesys2 FPGA boards. We are going to use the Pulpissimo for that.
We would like to flash the test software to it and also if possible use some debugging software via JTAG.
Do you have any suggestion to use as JTAG-cable or debugging software, that you are going to support?
Do I need to use Genesys2 PMOD connectors to connect JTAG-cable or do you have any solid solutions for that?
If understood correctly debugging software is going to need OpenOCD support and that is coming Q2/2019 for Pulpissimo. Right?
Br,
Akim
RE: FPGA JTAG-cable and debugger sw - bluewww - 03-28-2019
Hi,
Quote:Do you have any suggestion to use as JTAG-cable or debugging software, that you are going to support?
On the genesys2 I see two options:
1. Don't use any jtag cable but reuse the already existing FTDI chip through the micro USB port (labelled jtag). The FTDI chip exposes a second serial link that is routed to GPIO pins on the FPGA. You can use that and connect it to the PULPissimo jtag.
2. Use an Olimex adapter (like Olimex Ltd. ARM-USB-OCD-H JTAG+RS232), connect it to the PMOD connectors.
Regarding software we generally support gdb. As for the bridge that is required to allow gdb to talk to PULPissimo, the current master branch of PULPissimo (version 1.0.2 onwards) uses our own debug bridge to handle gdb connections. This is because these versions still use our custom debug unit.
For the new debug unit see below.
Quote:If understood correctly debugging software is going to need OpenOCD support and that is coming Q2/2019 for Pulpissimo. Right?
Indeed PULPissimo is going to have a compliant (riscv-debug-spec v0.13.1) debug unit and we intend to make it work with riscv-openocd out of the box.
Q2/2019 sounds about right, infact most things (gdb, openocd) are already working on the dbg_dev branch.
Regards,
bluewww
RE: FPGA JTAG-cable and debugger sw - Akim - 04-15-2019
Hello,
Thank You. We got it working by using Genesys2 on board FTDI chip (1.).
But then suddenly it did not work.
Error message:
FATAL ERROR: the command 'reset' has failed with an exception: Failed to initiate cable with error: Could not connect to JTAG device
On Genesys2 there is this chip: https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf
https://github.com/pulp-platform/pulp-debug-bridge#supported-cables
"Supported cables
2 FTDI cables are supported: --cable=ftdi@olimex and --cable=ftdi@digilent. However the bridge may need few modifications depending on the ftdi chip which is used."
Does this chip which is on Genesys2 board require any special settings or modifications?
Br,
Akim
RE: FPGA JTAG-cable and debugger sw - Akim - 04-16-2019
Trace:
Traceback (most recent call last):
File "/home/mijkau/Work/debug/pulp-builder/install/ws/bin/plpbridge", line 439, in <module>
handle_commands(bridge)
File "/home/mijkau/Work/debug/pulp-builder/install/ws/bin/plpbridge", line 425, in handle_commands
if commands.get(cmd)[1](bridge) != 0:
File "/home/mijkau/Work/debug/pulp-builder/install/ws/bin/plpbridge", line 213, in reset
return bridge.reset()
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 343, in reset
self.get_cable().jtag_reset(True)
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 199, in get_cable
self.__mount_cable()
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 184, in __mount_cable
self.__mount_ctype_cable()
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 194, in __mount_ctype_cable
system_config = self.config
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 85, in __init__
raise Exception('Failed to initialize cable with error: ' + self.module.bridge_get_error().decode('utf-8'))
Exception: Failed to initialize cable with error: Could not connect to JTAG device
RE: FPGA JTAG-cable and debugger sw - bluewww - 04-17-2019
(04-16-2019, 10:09 AM)Akim Wrote: Trace:
Traceback (most recent call last):
File "/home/mijkau/Work/debug/pulp-builder/install/ws/bin/plpbridge", line 439, in <module>
handle_commands(bridge)
File "/home/mijkau/Work/debug/pulp-builder/install/ws/bin/plpbridge", line 425, in handle_commands
if commands.get(cmd)[1](bridge) != 0:
File "/home/mijkau/Work/debug/pulp-builder/install/ws/bin/plpbridge", line 213, in reset
return bridge.reset()
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 343, in reset
self.get_cable().jtag_reset(True)
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 199, in get_cable
self.__mount_cable()
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 184, in __mount_cable
self.__mount_ctype_cable()
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 194, in __mount_ctype_cable
system_config = self.config
File "/home/mijkau/Work/debug/pulp-builder/install/ws/python/bridge/default_debug_bridge.py", line 85, in __init__
raise Exception('Failed to initialize cable with error: ' + self.module.bridge_get_error().decode('utf-8'))
Exception: Failed to initialize cable with error: Could not connect to JTAG device
Does this problem still persist or was it a configuration error on your side?
RE: FPGA JTAG-cable and debugger sw - Akim - 04-26-2019
Yes, it seems some kind of configuration problem.
We got one virtual Linux machine working, but another desktop Linux is not working and we got that "Python36 is crashed" on it.
Br,
Akim