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+--- Thread: clock problem when writing sdc file in order to synthesize PULPino (/showthread.php?tid=94)
clock problem when writing sdc file in order to synthesize PULPino - zhouqiang - 05-08-2019
Clock problem when writing sdc file in order to synthesize PULPino
I am now trying to write a constraint file (sdc file) to synthesize PULPino （using DC）, but I don't know much about PULPino's RTL design， so it is a challenging task for me，my question is：
1. According to the .xdc file in vivado, I infer that PULPino has three asynchronous clocks clk, spi_clk_i, tck_i. What is the frequency relationship between them?
2. In DC, I use the command get_nets/ports *clk*, I also got a spi_master_clk_o, which looks like an output port. What is it used for? Do I need to constrain it?
3. In the ASIC design, I want to set the frequency of the main clock clk to 100MHz. So, how should I set the frequency for the other two clocks?
4. In addition, I also want to constrain the generated clock. Is there a generated clock in PULPino? How should I find out all the generated clocks and the corresponding source clock?
RE: clock problem when writing sdc file in order to synthesize PULPino - kgf - 05-08-2019
There is a single clock in PULPino (clk). The SPI slave port (as definition of SPI) would have a clock input, so the slave will have to synchronize to this clock. tck I believe is the JTAG or test clock. You can decide how you want to constrain them.
Just as the slave has a clock in (which gets the clock from master), for the SPI master, this time you provide a clock signal. This is also your decision. In most cases you can use a divided clock from the main clock.
For these you can set them as needed (what SPI peripherals are you planning, how fast are they, what do they support)?
You might use generated clock in an actual implementation, depending on how you get the clock (i.e. you have an internal clock divider / PLL that is a black box). You do not have to do it if it is not needed.
RE: clock problem when writing sdc file in order to synthesize PULPino - zhouqiang - 05-09-2019
(05-08-2019, 03:21 PM)kgf Wrote: There is a single clock in PULPino (clk). The SPI slave port (as definition of SPI) would have a clock input, so the slave will have to synchronize to this clock. tck I believe is the JTAG or test clock. You can decide how you want to constrain them.
Just as the slave has a clock in (which gets the clock from master), for the SPI master, this time you provide a clock signal. This is also your decision. In most cases you can use a divided clock from the main clock.
For these you can set them as needed (what SPI peripherals are you planning, how fast are they, what do they support)?
You might use generated clock in an actual implementation, depending on how you get the clock (i.e. you have an internal clock divider / PLL that is a black box). You do not have to do it if it is not needed.
hello，
Thank you for your reply, it really helped me. And I want to ask, do I need to create a generated clock for "spi_master_clk_o"? It semms that spi_master_clk_o is a generated clock whose source clock is the main clock "clk" , but at the same time, it is also an output port. So I am tangled whether I should create a generated clock for it.