+- PULP Community (https://pulp-platform.org/community)
+-- Forum: PULP's Community forum (https://pulp-platform.org/community/forumdisplay.php?fid=1)
+--- Forum: PULP General questions (https://pulp-platform.org/community/forumdisplay.php?fid=2)
+--- Thread: How to do post-synthesis simulation of PULPino after generating netlist using DC (/showthread.php?tid=96)
How to do post-synthesis simulation of PULPino after generating netlist using DC - zhouqiang - 05-09-2019
Hello，
We want to tape out PULPino using SMIC 0.13um technology, and now we have finished DC and got netlist of PULPino, we have generated a 32KB SRAM macro ,the ROM macro and their function mode verilog file. Next, we are going to use the netlist, the RAM and ROM to do a post-synthesis simulation of PULPino. Can someone tell me how to perform post-synthesis simulation of PULPino? Especially, how to test the functions of SRAM and ROM to determine if they are working properly?
RE: How to do post-synthesis simulation of PULPino after generating netlist using DC - kgf - 05-09-2019
This is really not a PULP specific question, sorry.
RE: How to do post-synthesis simulation of PULPino after generating netlist using DC - zhouqiang - 05-10-2019
(05-09-2019, 03:20 PM)kgf Wrote: This is really not a PULP specific question, sorry.
Thank you for your reply, maybe I should post to the PULPino issue.