Pulpissimo Synthesis content - Printable Version +- PULP Community (https://pulp-platform.org/community) +-- Forum: PULP's Community forum (https://pulp-platform.org/community/forumdisplay.php?fid=1) +--- Forum: PULP General questions (https://pulp-platform.org/community/forumdisplay.php?fid=2) +--- Thread: Pulpissimo Synthesis content (/showthread.php?tid=98) |
Pulpissimo Synthesis content - MikkeN - 05-16-2019 Hi, I have reviewed Pulpissimo code. There is couple of issues (I try to synthesize it): 1. In pulp_soc.sv (line 861) is instatiation of module jtag_tap_top. However this module is not found. Instead there is module tap_top, should it be instantiated? 2. In soc_clk_rst_gen.sv there is three instatiations of gf22_FLL Comment says that it is not supported by FPGA Is this really synthesizable code? There is comments regarding that it is behavioral coding. Best Regards, MikkeN RE: Pulpissimo Synthesis content - fconti - 05-16-2019 1. Might be a recent name change, I saw some merge request with respect to that... will check 2. gf22_fll is just a stub for synthesis in an ASIC technology. For simulation you use a behavioral model ( I believe it’s called generic_fll). For synthesis of any kind you’ll have to provide your own clock generator (FLL or PLL). RE: Pulpissimo Synthesis content - MikkeN - 05-16-2019 (05-16-2019, 10:47 AM)fconti Wrote: 1. Might be a recent name change, I saw some merge request with respect to that... will check 2. Yes, that is what is also assumed. This FLL is instantiated for Soc_clk_reset_gen module and not bypassed in synthesis like it is in FPGA. So I will now make blackbox for that. RE: Pulpissimo Synthesis content - fconti - 05-16-2019 Rgd point 1: jtag_tap_top.sv is in pulpissimo/rtl/pulpissimo/jtag_tap_top.sv : https://github.com/pulp-platform/pulpissimo/blob/master/rtl/pulpissimo/jtag_tap_top.sv . It instantiates a couple modules taken from the jtag_pulp IP: https://github.com/pulp-platform/jtag_pulp . |