PULPissimo FLL bypass
#1
Hello everyone,
Could someone please help me bypass the FLL logic ? I want to use an external clock for my design.
At the moment, I have removed the gf22_FLL instances and tried to connect soc_clk and per_clk directly to ref_clk.
Could anyone please share their experience of bypassing the FLL ? How did you handle the rest of the logic present in soc_clk_rst_gen.sv file ?
With this, I get error captured in the attachment. 

Cheers


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Messages In This Thread
PULPissimo FLL bypass - by Supra - 10-30-2020, 03:33 PM
RE: PULPissimo FLL bypass - by heavySea - 11-02-2020, 07:38 AM
RE: PULPissimo FLL bypass - by Supra - 11-02-2020, 03:37 PM
RE: PULPissimo FLL bypass - by heavySea - 11-02-2020, 05:16 PM
RE: PULPissimo FLL bypass - by Supra - 11-02-2020, 08:41 PM
RE: PULPissimo FLL bypass - by Supra - 11-06-2020, 09:34 AM
RE: PULPissimo FLL bypass - by ivanhira - 06-03-2022, 07:23 PM
RE: PULPissimo FLL bypass - by Happybug - 02-06-2023, 02:00 PM

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