PULPissimo FLL bypass
#2
Hello Supra,

ref_clock has a frequency of 32.769kHz, which is generated e.g. by a quartz oscillator on a real chip. I think you could use this signal directly, but then you whole design will be not faster than this.
The error you have posted, shows, that the JTAG process failed during the memory write/read test. My guess is, that you probably need to slow down the JTAG clock in the testbench, since it is way to fast for the memory of the design.
You can extend the period in the task "jtag_wait_halfperiod" of "jtag_pkg.sv".

If your design needs to run faster than of 32.769kHz, you could add and expose one or two more clock inputs at the top module and propagate them to the soc_clk_rst_gen. You can then generate the clock signals in the testbench, just like it has been done with the ref_clk.

I hope this will help you.

Kind regards.
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Messages In This Thread
PULPissimo FLL bypass - by Supra - 10-30-2020, 03:33 PM
RE: PULPissimo FLL bypass - by heavySea - 11-02-2020, 07:38 AM
RE: PULPissimo FLL bypass - by Supra - 11-02-2020, 03:37 PM
RE: PULPissimo FLL bypass - by heavySea - 11-02-2020, 05:16 PM
RE: PULPissimo FLL bypass - by Supra - 11-02-2020, 08:41 PM
RE: PULPissimo FLL bypass - by Supra - 11-06-2020, 09:34 AM

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