PULPissimo FLL bypass

[Supra]

Hello heavySea,

Thank you very much for your reply. I currently see the following cases:

Case 1:  Original setup, no modifications to source code or tb
Works as expected. Hello world test passes. No problems.

Case 2:  FLL instantiations removed. No modifications to clocks
I removed the FLLs and instead used something like the following to propagate the clocks  in soc_clk_rst_gen.sv

Code:

            //SoC Clock
        assign s_clk_fll_soc = ref_clk_i;
           assign s_clk_soc = s_clk_fll_soc;
           assign soc_fll_slave_r_data_o = 'b0;
           assign soc_fll_slave_ack_o = 1'b1;
           assign soc_fll_slave_lock_o = 1'b1;

But this results in the problem mentioned at the top of this thread.
So, I tried changing "jtag_wait_halfperiod" from 50000 to 5000000 (x100 times slower !). With this modification, I do not see the reg access error (as shown in the original post).  But my simulation gets stuck at "Waiting for  end of computation". 

Case 3: FLL instantiations removed. Separate clocks for soc and jtag in test bench
I introduced a new net to distribute a faster clock to tmp_clk_ref when JTAG is not in action. This allows me to keep "jtag_wait_halfperiod" at the original 50000. This time too I get stuck at "Waiting for  end of computation". The change to soc_clk_rst_gen.sv is same as in case 2.

Have you faced this problem too? What logic is soc_clk_rst_gen.sv supposed to mimic if we do not use FLLs ?

Best Regards,
Supra