Building an RTL simulation platform Error

[RiscV]

Hi,
I followed the readme file of pulpissimo  for building an RTL simulation platform. After the following steps

Code:

source setup/vsim.sh

make build

I am getting error like this

Code:

make -C ../rtl/tb/remote_bitbang all
make[2]: Entering directory '/opt/pulpissimo/rtl/tb/remote_bitbang'
cc -MT remote_bitbang.o -MMD -MP -MF ./.d/remote_bitbang.Td -std=gnu11 -fno-strict-aliasing -Wall -Wextra -Wno-missing-field-initializers -Wno-unused-function -Wno-missing-braces -O2 -g -march=native -DENABLE_LOGGING -DNDEBUG -fPIC -I./  \
    -c  remote_bitbang.c -o remote_bitbang.o
ld -shared -E --exclude-libs ALL -o librbs.so  \
    remote_bitbang.o sim_jtag.o
make[2]: Leaving directory '/opt/pulpissimo/rtl/tb/remote_bitbang'
/opt/pulpissimo/sim//tcl_files/rtl_vopt.tcl
/usr/bin/env: ‘tclsh’: No such file or directory
Makefile:37: recipe for target 'opt' failed
make[1]: *** [opt] Error 127
make[1]: Leaving directory '/opt/pulpissimo/sim'
Makefile:47: recipe for target 'build' failed
make: *** [build] Error 2

 I am using ModelSim - Intel FPGA Edition 20.3 (includes Starter Edition).  Please help me ..