Post Synthesis Simulation in ASIC
The FLL is a clock generator, clock mux, clock gating and clock inverter are cells that are being instantiated from the technology libraries. The idea is to replace these 'behavioral' descriptions with the equivalent cells so that you can get something that works for your technology.

This is needed, as we are not allowed to disclose technology specific cells.

Note that the FLL is not strictly needed. Any clock source can be used. This would also change a bit the logic/bypass around the clocking solution which may have to be revised. Basically if you are designing a simpler/slower system you can also bring in the clock externally without something like PLL or FLL providing an internal solution.
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Post Synthesis Simulation in ASIC - by vignajeth - 04-07-2021, 12:23 PM
RE: Post Synthesis Simulation in ASIC - by kgf - 04-07-2021, 12:34 PM

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