01-10-2022, 03:56 PM
Hello KGF.
I have been doing some synthesis runs for FPGA, in particular, I have been using Genesys2 board for my investigation. At the moment, current maximum frequency that is achievable in the FPGA synthesis is lower than 40MHz. I have noticed that the critical path for the synthesis is actually the read path from the APB peripherals (assume it is failing in pready signal of the APB peripheral). My assumption is that it is failing because there are no registers between the prefetch buffer in the riscy and the APB peripheral, through different stages of the interconnects. I do not know about other paths, these are the ones that I found as failing paths when I ran the synthesis with 40MHz and after analyzing the reports files.
I first tried running 100MHz clk period, but the cycle slack was huge (might be that there were additional paths except the one that I mentioned before).
For my tests, I am using a relatively new version of Vivado, 2019.2.
Based on the previous reply from, I would assume I should be able to close the timing @60-80MHz, maybe even 100MHz for the FPGA. I might be doing something wrong but I am using FPGA build configs which are found on git. The one thing that is changed is actually clock frequency.
My intention right now is to understand if what I am trying to do is possible or not so that I can adjust accordingly. If achieving my target frequency for FPGA is completely of the table, I might settle to having an emulated system running at 30-40Mhz range.
Any suggestions on how to tackle this issue would be appreciated.
Thanks,
NK
I have been doing some synthesis runs for FPGA, in particular, I have been using Genesys2 board for my investigation. At the moment, current maximum frequency that is achievable in the FPGA synthesis is lower than 40MHz. I have noticed that the critical path for the synthesis is actually the read path from the APB peripherals (assume it is failing in pready signal of the APB peripheral). My assumption is that it is failing because there are no registers between the prefetch buffer in the riscy and the APB peripheral, through different stages of the interconnects. I do not know about other paths, these are the ones that I found as failing paths when I ran the synthesis with 40MHz and after analyzing the reports files.
I first tried running 100MHz clk period, but the cycle slack was huge (might be that there were additional paths except the one that I mentioned before).
For my tests, I am using a relatively new version of Vivado, 2019.2.
Based on the previous reply from, I would assume I should be able to close the timing @60-80MHz, maybe even 100MHz for the FPGA. I might be doing something wrong but I am using FPGA build configs which are found on git. The one thing that is changed is actually clock frequency.
My intention right now is to understand if what I am trying to do is possible or not so that I can adjust accordingly. If achieving my target frequency for FPGA is completely of the table, I might settle to having an emulated system running at 30-40Mhz range.
Any suggestions on how to tackle this issue would be appreciated.
Thanks,
NK