04-03-2025, 11:36 AM
Can you let us know where you are stuck, the original question had issues during synthesis. Is this the case for you as well. At what stage are you stuck, which branch are you using, which FPGA you are using?
AFAIK this is something that is working in our environment and is in active use.
AFAIK this is something that is working in our environment and is in active use.
Visit pulp-platform.org and follow us on twitter @pulp_platform