04-09-2019, 12:28 PM
Hello,
I have been trying to Synthesize and implement Pulpissimo on Xilinx FPGA using Vivado . There are problems in the syntesized design although elaborated design seems to be Okay. Have you synthesised Pulpissimo using VIvado and if yes then did you have to do changes to the RTL?
My synthesis basically is completed succesfully, but when I look at the synthesised schematics I can see that for example zynq_clk_i is not connected anywhere, although it should go to ref_clk_i in soc_domain.
Regards, Sirpa
I have been trying to Synthesize and implement Pulpissimo on Xilinx FPGA using Vivado . There are problems in the syntesized design although elaborated design seems to be Okay. Have you synthesised Pulpissimo using VIvado and if yes then did you have to do changes to the RTL?
My synthesis basically is completed succesfully, but when I look at the synthesised schematics I can see that for example zynq_clk_i is not connected anywhere, although it should go to ref_clk_i in soc_domain.
Regards, Sirpa