05-08-2019, 08:23 AM
Hello MikkeN,
Thank you so much for your generous help! Have you tried generating SRAM and boot_rom? Then after the DC is completed, have you simulated it with the generated netlist? How should the simulation after this be done?
Thank you so much for your generous help! Have you tried generating SRAM and boot_rom? Then after the DC is completed, have you simulated it with the generated netlist? How should the simulation after this be done?