Pulpissimo L2 memory access via JTAG
#4
(05-08-2019, 03:44 PM)pschiavo Wrote:
(05-08-2019, 07:41 AM)skor Wrote: Hello,

I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR        32'h1C00_0000
`define SOC_L2_END_ADDR          32'h1FFF_FFFF


However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from  any memory address that i have tried.
So where is the memory located actually ? 
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.

As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.

Regards, skor

Hello skor,


to read/write L2 memory with the JTAG please refer to these memory ranges between line 260 and 264

https://github.com/pulp-platform/pulp_so...ct.sv#L260

As far as I can tell, you should be able to R/W from 1c00_0000 so it is strange that you see all 0s.

The L2 memory is organized as 3 banks, of which one is interleaved.

The 3 banks have the following ranges:

Bank0: [1C00_0000, 1C00_8000)
Bank1: [1C00_8000, 1C01_0000)
Bank Interleaved: [1C01_0000, 1C08_2000)

you may want to try to read and write to the same bank to see whether it works. I can tell that in all our implementations on Silicon this has always worked so far Smile

Best
Davide

Hello,

I have now started to do RTL simulations with QUESTAsim  , for being able to look inside Pulpissimo. I am running the tb_pulp.sv test which according to simulation transcript is filling L2 memory (message 'loading L2 with JTAG interface') . I have waved all signals in L2 interface, but see no changes in address . Address L2_a_o is actually in 0x7000 all the time for all 4 banks ( there are 4 banks , not 3 as you told in your reply, which is again a bit confusing)  , but I am aware of the offset L2_OFFSET_PRI set thre in line 661 of soc_interconnect.sv

I took DBG_RX_add_i  bus to waves also in simulator ( soc_interconnect.sv). there seems to be the address chanings according to what is happening in test bench. 

Is the some parameter or definition somewhere which I should change to get the accesses going to L2 instead of somewhere else ( where?) . Do I have a wrong configuraion for the whole design and how should i modify it?

Regards , skor
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Messages In This Thread
Pulpissimo L2 memory access via JTAG - by skor - 05-08-2019, 07:41 AM
RE: Pulpissimo L2 memory access via JTAG - by kgf - 05-08-2019, 08:45 AM
RE: Pulpissimo L2 memory access via JTAG - by skor - 05-20-2019, 10:03 AM

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