Pulpissimo Synthesis content
#1
Hi, 

I have reviewed Pulpissimo code. There is couple of issues (I try to synthesize it):

1. In pulp_soc.sv (line 861) is instatiation of module jtag_tap_top. However this module is not found. Instead there is module tap_top,
should it be instantiated?

2. In soc_clk_rst_gen.sv there is three instatiations of gf22_FLL
Comment says that it is not supported by FPGA
Is this really synthesizable code?
There is comments regarding that it is behavioral coding.

Best Regards,
MikkeN
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Messages In This Thread
Pulpissimo Synthesis content - by MikkeN - 05-16-2019, 10:42 AM
RE: Pulpissimo Synthesis content - by fconti - 05-16-2019, 10:47 AM
RE: Pulpissimo Synthesis content - by MikkeN - 05-16-2019, 11:24 AM
RE: Pulpissimo Synthesis content - by fconti - 05-16-2019, 06:03 PM

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