08-23-2019, 11:36 AM
Hi,
we have synthesized Pulpissimo with Vivado (2018.3) to FPGA and with Design Compiler (2018) to silicon technology.
Now Pulpissimo code has been changed so, that Design Compiler can't synthesize it anymore.
Vivado synthesize it without issues.
Module LZC gives syntax error from this statement:
assign cnt_o = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : $clog2(WIDTH)'(0);
Also there is number of bus with conflicts which are quite painful to correct by user.
Can you make code cleaning and check that it passes Design Compiler?
I am also worried about quality of results in FPGA, because Vivado has not seen issues which exist.
we have synthesized Pulpissimo with Vivado (2018.3) to FPGA and with Design Compiler (2018) to silicon technology.
Now Pulpissimo code has been changed so, that Design Compiler can't synthesize it anymore.
Vivado synthesize it without issues.
Module LZC gives syntax error from this statement:
assign cnt_o = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : $clog2(WIDTH)'(0);
Also there is number of bus with conflicts which are quite painful to correct by user.
Can you make code cleaning and check that it passes Design Compiler?
I am also worried about quality of results in FPGA, because Vivado has not seen issues which exist.