PULPissimo FLL bypass
Hi heavySea,

Thank you very much for your reply. 
Quote:But you should make sure, that the clocks are not active during resets, e.g. by

I did this but it did not really help. 

Quote:Have you checked, if the core or any peripheral is still doing something? What program did you run? How does it print it's outputs? stdout or UART?

I could not verify if something else was running at the time. I ran the "hello world" C program present in the rt-examples repo (https://github.com/pulp-platform/pulp-rt-examples). It prints using stdout.

Quote:But you might want to have a separate clocks for SoC/CPU and peripherals (like there are two FLL's in the original design)
I have done this. The code that I have divides the per_clock by 2 with respect to SoC using a simple clock divider logic.  So, two of the many outputs coming out of soc_clk_rst_gen`s instantiation are clk_soc_o (freq same as ref_clk_i) and clk_per_o (freq half of ref_clk_i).

Quote:It should not matter if JTAG is in action. Where does temp_clk_ref source from? What does it drive?
Sorry for being very unclear here. What I should have mentioned was that in tb_pulp.sv, we have the following section:
        tmp_rst_n      = s_rst_dpi_n;
        tmp_clk_ref    = design_s_clk_ref; //Use faster clock
        tmp_trstn      = w_bridge_trstn;
        tmp_tck        = w_bridge_tck;
        tmp_tdi        = w_bridge_tdi;
        tmp_tms        = w_bridge_tms;
        tmp_tdo        = w_tdo;
        tmp_bridge_tdo = w_tdo;

     end else if (ENABLE_OPENOCD) begin
        tmp_rst_n         = s_rst_n;
        tmp_clk_ref       = s_clk_ref; //uses JTAG freq clock
        tmp_trstn         = sim_jtag_trstn;
        tmp_tck           = sim_jtag_tck;
        tmp_tdi           = sim_jtag_tdi;
        tmp_tms           = sim_jtag_tms;
        tmp_tdo           = w_tdo;
        tmp_bridge_tdo    = w_tdo;
        sim_jtag_enable = 1'b1;

     end else begin
        tmp_rst_n      = s_rst_n;
        tmp_clk_ref    = design_s_clk_ref; //ises fast clock
        tmp_trstn      = s_trstn;
        tmp_tck        = s_tck;
        tmp_tdi        = s_tdi;
        tmp_tms        = s_tms;
        tmp_tdo        = w_tdo;
        tmp_bridge_tdo = w_tdo;

The s_clk_ref is generated using the following :
tb_clk_gen #( .CLK_PERIOD(REF_CLK_PERIOD) ) i_ref_clk_gen (.clk_o(s_clk_ref) );

where REF_CLK_PERIOD is 30517ns. Since this is too slow for my normal logic, I use 
parameter  DESIGN_REF_CLK_PERIOD = 5ns;
tb_clk_gen #( .CLK_PERIOD(DESIGN_REF_CLK_PERIOD) ) i_design_ref_clk_gen (.clk_o(design_s_clk_ref) );

I may have misunderstood this part of the test bench.  When I say JTAG is in action, I mean I allow  tmp_clk_ref to take the clk generated with REF_CLK_PERIOD when ENABLE_OPENOCD is true.

Quote:Then have a look at the core where it gets stuck. The program counter would be a good start to look at.

Just out of curiosity, which core are you using? Ibex or Riscy?

 I will have a look at the program counter now. Thank you very much for the pointer !
I am using Riscy. 

My ultimate goal is to tape out Pulpissimo. We do not have an FLL and I am stuck at this point of bypassing it. It would be awesome if you (or your team) could share the experience of working without an FLL. I am very thankful to you for guiding so far !


Messages In This Thread
PULPissimo FLL bypass - by Supra - 10-30-2020, 03:33 PM
RE: PULPissimo FLL bypass - by heavySea - 11-02-2020, 07:38 AM
RE: PULPissimo FLL bypass - by Supra - 11-02-2020, 03:37 PM
RE: PULPissimo FLL bypass - by heavySea - 11-02-2020, 05:16 PM
RE: PULPissimo FLL bypass - by Supra - 11-02-2020, 08:41 PM
RE: PULPissimo FLL bypass - by Supra - 11-06-2020, 09:34 AM
RE: PULPissimo FLL bypass - by ivanhira - 06-03-2022, 07:23 PM
RE: PULPissimo FLL bypass - by Happybug - 02-06-2023, 02:00 PM

Forum Jump:

Users browsing this thread: 1 Guest(s)