02-25-2021, 06:10 PM

Hi,

I ran the cv32e40p (RI5CY) core with FPU (floating point) enabled and tried to check the result for all the floating-point operations. I have faced the following issues incase of division and fused operations.

I ran the cv32e40p (RI5CY) core with FPU (floating point) enabled and tried to check the result for all the floating-point operations. I have faced the following issues incase of division and fused operations.

- Rounding mode output is incorrect for division, rounding mode for the division is not the same as addition, subtraction, and multiplication

For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit. - Exception status flags output is incorrect for division, exception status flags output for the division is not the same as addition, subtraction, and multiplication, and doesn't follow IEEE754

For example, the overflow flag is not generated even if the division result generated is infinity (for MAX/MIN case). - Rounding mode output is incorrect for fused operations, rounding mode for fused operations is not the same as addition, subtraction, and multiplication

For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit. - Getting output as X in fused operations if any of the operands is 0

For example, If any of the 3 operands are 0 in FMA, the result generated by the core is X.