Synthesis failed on ZedBoard (riscv_ex_stage.sv)

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Synthesis failed on ZedBoard (riscv_ex_stage.sv)

dah29

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Posts: 5
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Joined: Mar 2021

#5

03-24-2021, 03:10 PM

Hi, I invoked Vivado through the zedboard Makefile ("make zedboard").It seems that the Xillinx IPS are built because I locate pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci but I don't know why the file is not found....

I attach the log files

Attached Files
.txt

.txt

xilinx_slow_clk_mngr_log.txt (Size: 29.42 KB / Downloads: 1)
.txt

.txt

xilinx_private_ram_log.txt (Size: 25.63 KB / Downloads: 0)
.txt

.txt

xilinx_interleaved_ram_log.txt (Size: 25.94 KB / Downloads: 1)
.txt

.txt

xilinx_clk_mngr_log.txt (Size: 26.61 KB / Downloads: 1)
.txt

.txt

pulpisimo-zedboard_log.txt (Size: 48.17 KB / Downloads: 4)

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Synthesis failed on ZedBoard (riscv_ex_stage.sv) - by dah29 - 03-23-2021, 06:53 PM

RE: Synthesis failed on ZedBoard (riscv_ex_stage.sv) - by akurth - 03-24-2021, 07:08 AM

RE: Synthesis failed on ZedBoard (riscv_ex_stage.sv) - by dah29 - 03-24-2021, 09:59 AM

RE: Synthesis failed on ZedBoard (riscv_ex_stage.sv) - by akurth - 03-24-2021, 01:14 PM

RE: Synthesis failed on ZedBoard (riscv_ex_stage.sv) - by dah29 - 03-24-2021, 03:10 PM

RE: Synthesis failed on ZedBoard (riscv_ex_stage.sv) - by akurth - 03-25-2021, 09:56 AM

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