looking at website, I see several cores have been taped out.
I'm trying to find more info in how tape out has been carried out.
Is the tape out flow fully based on the RTL of the cores (the one available on GitHub repos) or human circuit customization has been
performed ?
For example, looking at https://github.com/openhwgroup/cv32e40p core I see the register file is described at high level as a simple array.
When it comes to circuit implementation has the synthesis  had free room to decide how to translate the RF in real digital circuit or some human
customization has been carried out?

Messages In This Thread
PULP CORE TAPE OUT - by giumaug - 09-29-2022, 08:09 AM
RE: PULP CORE TAPE OUT - by kgf - 09-29-2022, 08:38 AM

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