Who uses PULP

This is the list of technology companies, NGOs and academic institutions that currently use PULP. Does your company or institution use PULP? Please, contact us. We would love to add you to our list.

Industrial users


IBM has been using our 32-bit PULPino as a starting point for their Next-Generation Edge Computing project, as presented at the RISC-V workshop 2018 in Barcelona. See the slides and the video from the talk by Seiji Munetoh.

Google has been using our RI5CY for Pixel Visual Core, highlighting its SolderPad license and SystemVerilog implementation. For more information watch this video and slides by Matt Cockrell at the RISC-V workshop 2018 in Barcelona.

GreenWaves Technologies developed a fully-programmable near-sensor analytics IoT application processor GAP8 based on our PULP. Learn more about GAP8 on their website. and from this presentation by Eric Flamand.

NXP has been collaborating with PULP Platform on our 32-bit PULPino. See the slides and the video from the talk by Rob Oshana at the RISC-V workshop 2018 in Barcelona.

Dolphin Integration, a leader in energy-efficient IPs is using an adapted version of our Zero-riscy in their RISC-V subsystem called RV32 Tornado. Read more about it on their website.

CEVA-DSP, the licensor of signal processing platforms and IoT processors, started using our Zero-riscy to offer turnkey hardware platforms with FreeRTOS and communication stacks running on it. Find out more.

IQ-Analog taped out a GLOBALFOUNDRIES 14nm ADC/DAC test chip with a RI5CY core+ 256K instruction and 128K data SRAM. There seems to be a follow-up with 2 RI5CYs, as well. Learn more.

Mentor uses our PULPino microcontroller system because it allows them to showcase their tools without being encumbered by licensing restrictions.



Cadence uses PULPino as a reasonably-sized design for their training modules for their EDA tools without having to worry about license restrictions.



QuickLogic collaborates with ETH Zurich on eFPGA integration into PULP platform. The fully integrated system with eFPGA is expected to be available Q1' 2019. Learn more.

STMicroelectronics collaborated with PULP platform to showcase their FD-SOI technology. More on this can be found in the paper 'Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster'.

GLOBALFOUNDRIES has a direct collaboration agreement with PULP for exploring design methodologies in their 22 FDX technologies. A joint presentation with PULP can be found here.

lowRISC works in close collaboration with PULP and uses PULP's components and processor cores. Explore more on GitHub.


Valtrix recently enabled their IP/SoC verification platform on the open source test bench of PULPino. Learn more.


Embecosm has been using PULP cores in their projects. They have made several contributions to fix issues in our cores and forked our RI5CY for Verilator and GDB server development.

Direct research collaborators on PULP

  • Politecnico di Torino
  • University of Cambridge
  • USI Lugano
  • TU Kaiserslautern
  • University of Cagliari
  • IBM Research Zurich
  • EPF Lausanne
  • CSEM Neuchatel
  • Princeton University
  • Technische Universität Graz
  • CEA-Leti Grenoble
  • Fraunhofer-Gesellschaft
  • Sapienza Università di Roma

Academic users we are aware of

  • Università di Genova
  • Politecnico di Milano
  • Fondazione Bruno Kessler
  • Lund University
  • Stanford University
  • UC Los Angeles
  • UC San Diego
  • Columbia University
  • Universitat Bar-Ilan
  • İstanbul Teknik Üniversitesi
  • NCTU Hsinchu
  • University of Zagreb, FER
  • TUT Tampere
  • RWTH Aachen
  • IST University of Lisboa
  • UFRN Rio Grande do Norte
  • TU Darmstadt
  • Universität Bremen
  • Hongik University Seoul
  • IIT Kharagpur
  • LIRMM Montpelier
  • University of Stuttgart
  • University of Tübingen