PULP Team


Luca Benini

Benevolent Dictator for Life and overall inspirator of the PULP Platform project.


Davide Rossi

Project Leader responsible for the overall architectural development and for ASIC backend implementation. Main responsible for the DMA IP.

Francesco Conti

PULP “evangelist” and leader of HW acceleration and near sensor analytics efforts.


Frank K. Gürkaynak

Main responsible for EDA tools used for PULP development, for ASIC testing and for PULP didactic usage.

Andrea Cossettini

Andrea leads efforts in ultrasound and manages the Future Computing Lab (EFCL).

Ahmad Mirsalari

Ahmad works on ML for Approximate Computing, studying variable- and mixed-precision computing techniques to improve energy efficiency.


Alessandro Capotondi

Co-designer of the OpenMP parallel programming runtime for PULP.


Alessandro Marchei

Alessandro works on neuromorphic perception for robotics.


Alessandro Nadalini

Alessandro works on RISC-V ISA extensions dedicated to the acceleration of mixed-precision QNNs inference on PULP clusters.


Alessandro Ottaviano

Alessandro researches the next generation Snitch based PULP systems.


Alessio Burello

Co-developer of DORY (Development Oriented to memoRY) framework for deep neural network execution on PULP.

Amirhossein Kiamarzi

Amirhossein focuses on modeling hardware processors, accelerators and vector processor applications on GVSoC.


Andrea Belano

Andrea works on the development of accelerators for Artificial Intelligence applications on energy-efficient platforms.

Andreas Kurth

1st Lieutenant of the group, keeper of HERO, the big PULP.


Angelo Garofalo

Angelo is working on PULP-NN, an optimized library for QNN inference on PULP Clusters.


Anna Tegon

Anna works on Machine Learning applications.


Antonio Pullini

Lead designer of all PULP external interfaces and of the uDMA subsystem. The go-to person for ASIC backend implementation.

Arpan Prasad

Arpan will work on hardware accelerator design for Machine Learning Applications.



Benedetta Mazzoni

Benedetta works on ML algorithms and systems for bio applications in real-time optimized for PULP.

Bowen Wang

Bowen designs flexible manycore systems for AI workload deployment.


Chaoqun Liang

Chaoqun works on on-chip and off-chip communication.



Chi Zhang

Chi works on memory systems and interfaces. His interests include HPC architectures, energy-efficient HW and heterogenous architectures.

Cristian Cioflan

Cristian aspires to become the master of ML on constrained embedded devices and strives to bring "Aha!" moments to our students.

Christoph Leitner

Christoph's research is focused on ultrasound applications.



Christopher Reinwardt

works on heterogeneous platforms with manycore accelerators and SoCs, focusing on performance and non-functional properties.

Cyril Koenig

Cyril works on our heterogenous HPC architecture. His interests include SoC design and low level programming.

Cyrill Durrer

Cyrill works on NN accelerators and design verification.



Daniele J. Pagliari

Daniele collaborates with PULP on firmware and software projects for PULP devices.

Daniele Palossi

Daniele researches deep learning applications for PULP-based autonomous flying drones.

Danilo Cammarata

Danilo focuses on advancing Vector Processing Units for edge AI applications.


Davide Nadalini

In an effort to make things smart(er), Davide develops On-Device Learning applications for PULP.

Diyou Shen

Diyou works on fault tolerant, reliability and predictibility on interconnection.

Enrico Zelioli

Enrico works on the virtualization solutions for RISC-V mixed-criticality systems.


Gamze Islamoglu

Gamze works on hardware architectures for machine learning applications.


Germain Haugou

Leader of all software integration efforts, main developer of the PULP hardware abstraction layer, runtime and SDK.

Giovanni Bambini

Giovanni uses PULP to keep microprocessors cool and fast, deploying control algorithms for thermal and power capping.


Giuseppe Tagliavini

Develops compiler extensions and exotic runtime environments for emerging computing paradigms. A space cowboy of embedded SW.

Giusy Spacone

Giusy works on wearable-ultrasound centric sensor-fusion strategies for human-machine interfaces.

Hong Pang

Hong currently focuses on PULP-based scalable hardware architecture for HPC.



Jonas Kühne

Jonas researches computer vision and perception for drone applications.

Julian Moosmann

Julian works on tinyML applications for PULP, especially using dynamic vision cameras.

Lorenzo Lamberti

Lorenzo works on drones.



Lorenzo Leone

Lorenzo works on heterogeneous scalable Hardware for Machine Learning applications.

Luca Bertaccini

Luca works on PULP based accelerators.


Luca Bompani

Luca is the developer of Ultra-low power machine learning based application.


Luca Colagrande

Luca researches efficient and scalable HPC systems.

Luka Macan

Luka is our Croatian PULP enthusiast who is working on tools for deployment of deep learning applications on our platforms.

Luigi Ghionda

Luigi works on hardware accelerators design for space PULP SoCs.


Maicol Ciani

Maicol's work is focused on security extensions to PULP SoCs.

Manuele Rusci

Designer of interfaces with ultra-low power sensors, and developer of related applications.

Marco Bertuletti

Marco implements DSP algorithms on PULP and parallelizes algorithms of 5G PUSCH channel on Mempool.


Marco Guermandi

Designer of PULP-based Human-Machine-Interfaces and related applications.


Massimo Micolitti

Massimo works on biosignals, LiDAR, Radar technology and RISC-V SW design with a dedicated focus on the automotive industry.

Matteo Perotti

Matteo works on PULP core development.




Mattia Orlandi

Mattia researches bioinspired approaches for developing ultra low-power Human-Machine Interfaces based on ExG signals.

Mattia Sinigaglia

Our peripheral's master. Mattia works on integrating and testing peripherals in PULP.


Michael Rogenmoser

Michael will be working on adding fault tolerance to PULP systems. He wants to be the first PULP member in space.


Navaneeth Kunhi Purayil

Navaneeth works on vector processing architectures for High Performance Computing.

Nils Wistoff

Nils works on securing RISC-V architectures and supporting Ariane development.

Paul Scheffler

Paul researches future PULP systems.




Philip Wiese

Philip focuses on the deployment of ML models on heterogeneous many-core systems and environmental sensing with on-device training capabilities.

Philipp Mayer

Philipp is going to develop embedded applications around PULP.


Philippe Sauter

Philippe works on open source EDA flows for digital designs targeting completely open PULP chips from RTL all the way to GDS.


Pierangelo Rapa

Pierangelo works on biosignals and ultra-low-power HMIs with specific emphasis on their application in the automotive industry.

Pirmin Vogel

Leads efforts to use PULP within a heterogeneous system architecture; designer of the Linux driver runtime for ARM based host systems.

Riccardo Fiorani

Riccardo works on physical aware design of heterogeneous PULP architectures in scaled technology nodes.


Riccardo Tedeschi

Riccardo works on extending PULP IPs to address safety critical applications.

Robert Balas

Robert works on debugging PULP.


Sergio Mazzola

He has been involved in the Ampere project working on multi-criterion optimization making the use of HERO.


Simone Manoni

Simone works on HW/SW acceleration for Sparse Neural Networks.

Thomas Benz

Thomas works on PULP cores.


Thorir Ingolfsson

Thorir works on Machine Learning applications.


Tim Fischer

Tim works on HPC systems for Machine Learning and AI workloads.


Tommaso Polonelli

Designer of multi-protocol wireless interfaces and developer of related applications.

Victor Jung

Victor tweaks algorithms so that they work on our newest platforms.



Victor Kartsch

Victor develops ultra low-power Human Machine Interaction applications based on EMG/EEG signals.

Viviane Potocnik

Viviane will be working on MiniFloat training on Snitch-based platforms and developing the software stack for novel hardware architectures.

Yawei Li

Our machine learning expert. Works on the development and deployment of multimodal foundation models.


Yichao Zhang

Yichao conducts his research in IC physical design.

Yvan Tortorella

Yvan works on developing computing architectures and accelerators for space applications.

Zexin Fu

Zexin works on cache systems, cache coherence and on-chip network design.


Past collaborators


Past collaborators
  • Sergei Vostrikov worked on ultrasound architectures.
  • Samuel Riedel worked on MemPool and the synchronization of manycore systems.
  • Nazareno Bruschi worked on quantized neural networks in extreme edge devices and GVSoC PULP Simulator.
  • Marcello Zanghieri worked on Deep Learning for HMI, researching models suitable for execution on ultra-low-power microcontrollers.
  • Mahyar worked on drone swarm applications and indoor localization.
  • Luca Valente worked on debugging PULP and testing peripherals.
  • Hanna Muller worked on drones and wind turbine monitoring.
  • Vlad Niculescu worked on drone applications
  • Moritz Scherer worked on ML accelerators
  • Alfio Di Mauro - worked on event-based computing and testing
  • Xiaying Wang - worked on programming PULP-based systems
  • Gianna Paulin - worked on machine learning applications
  • Moritz Schneider - worked on security extensions on PULP systems
  • Jannis Schönleber - worked on deep neural network acceleration
  • Matheus Cavalcante - worked on vector processing unit of PULP for HPC architectures
  • Manuel Eggimann - worked on ExG signal related biomedical applications
  • Matteo Spallanzani - worked on data analytics, ML, QNN and algorithmic optimizations
  • Florian Zaruba - designer of the PULPino Imperio chip, developer of Ariane, master of the Snitches
  • Stefan Mach - the ultimate master of the Floating Point Unit (FPU)
  • Michael Hersche - used to work on Machine Learning applications
  • Fabio Montagna - worked on human-computer interfaces based on ExG signals
  • Francesco Paci - works on Embedded Computer Vision at GreenWaves Technologies in Grenoble
  • Fabian Schuiki - standard-cell memory guru, hardware designer and tamer of the Snitches
  • Davide Schiavone - designer of the DSP extensions for the OR10N and RI5CY cores, and the RI5CY maintainer
  • Andrea Marongiu - co-designer of the OpenMP parallel programming runtime for PULP
  • Maxim Mattheuws - worked on predictable execution of PULP-based systems
  • Michael Schaffner - used to be the co-leader of the development of the shared FPU/LNU IPs for PULP and the main author of our logo
  • Michael Gautschi - used to be the leader of the PULPino project and of the development of the shared FPU/LNU. He was also one of the designers of the OR10N and RI5CY cores
  • Giovanni Rovere - worked on the VivoSoC project
  • Renzo Andri - original co-designer of the OR10N core
  • Eric Flamand - designer of our RISC-V ISA extensions for DSP and main developer of the enhanced GCC toolchain for RI5CY.
  • Igor Loi - lead designer of all internal interconnect IPs and of the cluster instruction cache, also the responsible for frontend ASIC synthesis.
Past student contributions
  • Andreas Traber - Designer and main maintainer of the RI5CY core, and original designer and maintainer of PULPino.
  • Sven Stucki - Original designer of the porting of OR10N to the RISC-V ISA, which became the RI5CY core.
  • Robert Schilling - Designer of encryption HW accelerator for the PULP platform.
  • Matthias Baer - Original co-designer of the OR10N core.