PULP Team


The hardware team

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Luca Benini

Benevolent Dictator for Life and overall inspirator of the PULP Platform project.


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Antonio Pullini

Lead designer of all PULP external interfaces and of the uDMA subsystem. The go-to person for ASIC backend implementation.

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Davide Rossi

Project Leader responsible for the overall architectural development and for ASIC backend implementation. Main responsible for the DMA IP.


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Fabian Schuiki

Standard-cell memory guru, hardware designer, supreme project gitler and tamer of the Snitches.

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Florian Glaser

Designer and maintainer of the new event unit in PULP.

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Francesco Conti

PULP “evangelist” and leader of HW acceleration and near sensor analytics efforts.


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Angelo Garofalo

Angelo is working on PULP-NN, an optimized library for QNN inference on PULP Clusters.

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Stefan Mach

Hail the boss of PULP boards and PCBs.


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Davide Schiavone

Designer of the DSP extensions for the OR10N and RI5CY cores, and the current RI5CY maintainer.


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Frank K. Gürkaynak

Main responsible for EDA tools used for PULP development, for ASIC testing and for PULP didactic usage.

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Alfio Di Mauro

Event-based computing expert and tester guru in the making.

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Florian Zaruba

Designer of the PULPino Imperio chip, developer of Ariane, master of the Snitches.


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Andreas Kurth

1st Lieutenant of the group, keeper of HERO, the big PULP.

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Moritz Schneider

Our expert for security extensions on PULP systems

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Matheus Cavalcante

Matheus works on vector processing unit of PULP for HPC architectures.



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Robert Balas

Robert works on debugging PULP.

Thomas Benz
Thomas Benz

New PULP member. Thomas will work on PULP cores.

Thomas Benz
Matteo Perotti

New PULP member. Matteo will work on PULP core development.



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Paul Scheffler

New member of the PULP team. He will be working on future PULP systems.

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Nils Wistoff

Nils works on securing RISC-V architectures and supporting Ariane development.



The software team

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Pirmin Vogel

Lead of all efforts to use PULP within a heterogeneous system architecture; designer of the Linux driver runtime for ARM based host systems.

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Germain Haugou

Leader of all software integration efforts, main developer of the PULP hardware abstraction layer, runtime and SDK.

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Alessandro Capotondi

Co-designer of the OpenMP parallel programming runtime for PULP.



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Andrea Marongiu

Co-designer of the OpenMP parallel programming runtime for PULP.


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Giuseppe Tagliavini

Develops compiler extensions and exotic runtime environments for emerging computing paradigms. A space cowboy of embedded SW.

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Alessio Burello

Co-developer of DORY (Development Oriented to memoRY) framework for deep neural network execution on PULP.




The applications team

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Victor Kartsch

Victor develops ultra low-power Human Machine Interaction applications based on EMG/EEG signals.

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Fabio Montagna

Our application guy working on human-computer interfaces based on ExG signals.

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Francesco Paci

Our French Connection. Works on Embedded Computer Vision at GreenWaves Technologies in Grenoble.


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Marco Guermandi

Designer of PULP-based Human-Machine-Interfaces and related applications.

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Daniele Palossi

One day he’s going to fly. Daniele is a PULP-based unmanned aerial vehicle aficionado.

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Tommaso Polonelli

Designer of multi-protocol wireless interfaces and developer of related applications.


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Manuele Rusci

Designer of interfaces with ultra-low power sensors, and developer of related applications.

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Xiaying Wang

Xia is going to work on programming PULP-based systems.

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Manuel Eggimann

Uses PULP for ExG signal related biomedical applications.


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Philipp Mayer

Philipp is going to develop embedded applications around PULP.

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Gianna Paulin

Gianna is working on machine learning applications.

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Michael Hersche

Michael is working on machine learning applications.


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Hanna Müller

New PULP member. Hanna will be working on drones and wind turbine monitoring.

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Samuel Riedel

New PULP member. Samuel will be working on HERO and on Mempool.

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Luca Bertaccini

New PULP member. Luca will be working on PULP based accelerators.


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Matteo Spallanzani

Postdoctoral researcher working on data analytics, ML, QNN and algorithmic optimizations.

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Moritz Scherer

New PULP member. Moritz will work on on ML accelerators.

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Maxim Mattheuws

Maxim works on predictable execution of PULP-based systems.


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Georg Rutishauser

Georg works on mixed-precision ML acceleration and compression techniques for deep-learning related memory transfers.

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Sergei Vostrikov

Sergei works on ultrasound architectures.


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Vlad Niculescu

Vlad works on drone applications.


Silent / Past collaborators


Current collaborators without a profile image
  • Eric Flamand - Designer of our RISC-V ISA extensions for DSP and main developer of the enhanced GCC toolchain for RI5CY.
  • Igor Loi - Lead designer of all internal interconnect IPs and of the cluster instruction cache. He is also the responsible for frontend ASIC synthesis.
Past collaborators
  • Michael Schaffner - He used to be the co-leader of the development of the shared FPU/LNU IPs for PULP and the main author of our logo.
  • Michael Gautschi - He was the leader of the PULPino project and of the development of the shared FPU/LNU. He was also one of the designers of the OR10N and RI5CY cores.
  • Giovanni Rovere - Worked on the VivoSoC project.
  • Renzo Andri - Original co-designer of the OR10N core.
Past student contributions
  • Andreas Traber - Designer and main maintainer of the RI5CY core, and original designer and maintainer of PULPino.
  • Sven Stucki - Original designer of the porting of OR10N to the RISC-V ISA, which became the RI5CY core.
  • Robert Schilling - Designer of encryption HW accelerator for the PULP platform.
  • Matthias Baer - Original co-designer of the OR10N core.