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i am trying to do some performance measurements on the Ariane processor and therefore, I would like to use the cycle count from the RDCYCLE instruction. My code compiles fine, however, if I run it, I get a “illegal instruction” error. The following is the critical code snippet (both the CSRRS and RDCYCLE lead to the same error)

unsigned long get_clk(){
    unsigned long timer = 0;
    //__asm__ volatile("CSRRS %[result], cycle, x0\n\t" : [result]"=r"(timer)::);
    __asm__("RDCYCLE %[result]\n\t" : [result]"=r"(timer)::);
    return timer;

The RISC-V “Instruction Set Manual II: Privileged Architecture” states that the cycle CSR entry should be readable from user mode. I figured that this might not be the case in Ariane which would be fine if I could get to supervisor mode somehow. I looked into writing a kernel module that would give me access to the performance measures. Unfortunately, this turned out to be quite challenging since I can neither compile code on the FGPA nor use insmod to install my kernel module. Is there an easy way to get access to the cycle timer?

Thank you!


-- Edit: The same happens if I just use the built-in C time() function...
This is from Florian (who is not yet on the board):

Ariane currently hardwires `[m|s]counteren` (`rdcycle` is a pseudo op for `csrr cycle`): "When the CY, TM, IR, or HPMn bit in the mcounteren register is clear, attempts to read the cycle, time, instret, or hpmcountern register while executing in S-mode or U-mode will cause an illegal instruction exception." Volume II: RISC-V Privilegd Architecture V1.12-draft, p. 35

Solution 1: Implement a trap handler in machine-mode software (probably `bbl`) which handles the illegal instruction (csr read) and reads from `mcycle` and reports back the result. Most of the trap handling infrastructure is already in place of the clint.

Solution 2: Implement `[m|s]counteren` which makes the bits readable in lower privilege levels. You need to make sure that machine mode software and supervisor mode software make them accessible.