PULP Community

Hello,

Out of curiosity, I'm learning more about the RI5CY core, especially the ex_stage. I read the Near-Threshold RISC-VCore With DSP Extensions for Scalable IoT Endpoint Devices paper and I got the core from the dedicated github page. Using Synopsys Design Compiler and the 28nm FD-SOI technology (the only technology available to me), I synthesized the multiplier (mult.sv) present in the RI5CY core. I obtain a maximum operating frequency of the multiplier of 200 MHz.

This frequency seems to me a little low. Considering the various documents I have seen on the internet, I would expect to obtain a frequency rather between 450 and 650 MHz.

Does anyone know if the maximum frequency of 200MHz is actually too low for the RI5CY core multiplier?


Thank you in advance.

STM28 FDSOI has many corners and flavors. It also depends a little bit on them. Unfortunately, NDAs would not allow me to comment on specific speed, but you are right the number is low from what you expect, it could be a lower power, lower leakage setup.

Also note that synthesis constraints can result in different implementations that exploit different trade-offs. Make sure your timing constraints and also putput loads are specified properly