PULP Community

Hello,

I am trying to generate pulpino's bitstream without using the processing system loading the programs via SPI SLAVE. I modified the pulpemu folder deleting all the processing system's part and I managed to generate the bitstream but I am getting this warnings:

WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0__0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__1 input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mac input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mul input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/p_0_out input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mac output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mul output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/p_0_out output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (ZPS7-1) PS7 block required - The PS7 cell must be used in this Zynq design in order to enable correct default configuration.

Then with Vivado I transfer the bitstream to the zedboard and send the code to load the program via SPI SLAVE but I don't get any answer from MISO and it doesn't load the program.

Any help?

First of all consider using PULPissimo not PULPino which was our first release many years ago.

The DPIP-1 DOPOP-1 warnings are performance related, they should not be an issue.

I am not so sure about the PS7 block. I think at the time, we used the PS block as part of the external communoication/debugger etc.. so it really should be part of the design.. I think using PULPIssimo would be a better solution..