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I tried to use DC to synthesize pulpino, but the following error occurred:

Error: ../input_data/control_tp.sv:34: Unable to open file `fpu_defs_div_sqrt_tp.pvk': in search_path {/home/ichip/Desktop/PULPino_scripts/DC/tmp . /eda/synopsys/syn_vH-2013.03/libraries/ Syn /eda/synopsys/syn_vH-2013.03/minpower/syn /eda/synopsys/syn_vH-2013.03/dw/syn_ver /eda/synopsys/syn_vH-2013.03/dw/sim_ver}. (VER-292)

I opened control_tp.sv and found line 34 is:

Import fpu_defs_div_sqrt_tp::*;

It seems that this sentence caused DC to make a mistake. Can someone help me to see what this sentence means? How should I solve this error? In addition, when using DC to synthesis pulpino, what should be noted?
I solved this problem, when analyze system Verilog,you should analyze packages first,so pick up packages in the RTL design and analyze them first, then the errors disappeared.