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Full Version: How to do post-synthesis simulation of PULPino after generating netlist using DC
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     We want to tape out PULPino using SMIC 0.13um technology, and now we have finished DC and got netlist of PULPino, we have generated a 32KB SRAM macro ,the ROM macro and their function mode verilog file. Next, we are going to use the netlist, the RAM and ROM to do a post-synthesis simulation of PULPino. Can someone tell me how to perform post-synthesis simulation of PULPino? Especially, how to test the functions of SRAM and ROM to determine if they are working properly?
This is really not a PULP specific question, sorry.
(05-09-2019, 03:20 PM)kgf Wrote: [ -> ]This is really not a PULP specific question, sorry.

Thank you for your reply, maybe I should post to the PULPino issue.