Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster PULP
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beignè, Fabien Clermidy, Philippe Flatresse and Luca Benini
IEEE Micro, 37 (5): 20-31, Piscataway, NJ: IEEE, 2017.
DOI: 10.1109/MM.2017.3711645

  PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision  PULP
Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi and Luca Benini
Journal of Signal Processing Systems, 84 (3): 339-354, Berlin: Springer, 2016
DOI: 10.1007/s11265-015-1070-9

  HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA BigPULP
Andreas Kurth, Pirmin Vogel, Alessandro Capotondi, Andrea Marongiu, Luca Benini
Proceedings of Computer Architecture Research with RISC-V Workshop (CARRV' 17), Boston, MA: 2017.
DOI: 10.3929/ethz-b-000219249

  μDMA: An autonomous I/O subsystem for IoT end-nodes  PULPissimo
Antonio Pullini, Davide Rossi, Germain Haugou and Luca Benini
2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Piscataway, NJ: IEEE, 2017
DOI: 10.1109/PATMOS.2017.8106971

  Near-Threshold RISC-V core with DSP extensions for scalable IoT endpoint devices  RI5CY
Michael Gautschi, Pasquale D. Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak and Luca Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (10): 2700-2713, New York, NY: IEEE, 2017.
DOI: 10.1109/TVLSI.2017.2654506

  Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications  Zero-riscy, Micro-riscy
Pasquale D. Schiavone, Francesco Conti, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand and Luca Benini
2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 8106976, Piscataway, NJ: IEEE, 2017.
DOI: 10.1109/PATMOS.2017.8106976

   Exploring Shared Virtual Memory for FPGA Accelerators with a Configurable IOMMU New
Pirmin Vogel, Andrea Marongiu, Luca Benini
IEEE Transactions on Computers, Early Access: 1-1, New York, NY: IEEE, 2018.
DOI: 10.1109/TC.2018.2879080

   High speed ASIC implementations of leakage-resilient cryptography Cryptography
Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gürkaynak, Michael Muehlberghuber, Luca Benini
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): 1259-1264, Piscataway, NJ: IEEE, 2018.
DOI: 10.23919/DATE.2018.8342208

   GAP-8: A RISC-V SoC for AI at the Edge of the IoT
Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini
2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP): 1-4, Piscataway, NJ: IEEE, 2018.
DOI: 10.1109/ASAP.2018.8445101

   The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores Building blocks
Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, Luca Benini
IEEE Transactions on Multi-Scale Computing Systems, 4(2): 99-112, New York, NY: IEEE, 2018.
DOI: 10.1109/TMSCS.2017.2769046

   A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems Applications (ExG)
Victor Javier Kartsch, Simone Benatti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
Information Fusion, 43: 66-76, Amsterdam, Elsevier BV, 2018.
DOI: 10.1016/j.inffus.2017.11.005

   A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics Accelerators / Heterogeneous Systems
Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi
2018 IEEE International Symposium on Circuits and Systems (ISCAS): 1-5, Piscataway, NJ: IEEE, 2018.
DOI: 10.1109/ISCAS.2018.8351749

   PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform Applications (ExG)
Fabio Montagna, Abbas Rahimi, Simone Benatti, Davide Rossi, and Luca Benini
Proceedings of the 55th Annual Design Automation Conference (DAC '18): 111:1-111:6, New York, NY: ACM, 2018.
DOI: 10.1145/3195970.3196096

   Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes Machine Learning
Erfan Azarkhish, Davide Rossi, Igor Loi and Luca Benini
IEEE Transactions on Parallel Distributed Systems, 29 (2): 420-434, New York, NY: IEEE, 2018.
DOI: 10.1109/TPDS.2017.2752706

  XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference Machine Learning Best Paper Award
Francesco Conti, Pasquale Davide Schiavone, Luca Benini
Accepted for presentation at CODES'18 and for publication in IEEE Transactions on Computer-Aided Design of Circuits and Systems (TCAD) as part of the ESWEEK-TCAD special issue
arXiv:1807.03010 [cs.NE]

  Ultra Low Power Deep-Learning-powered Autonomous Nano Drones Machine Learning Application
Daniele Palossi, Antonio Loquercio, Francesco Conti, Eric Flamand, Davide Scaramuzza, Luca Benini
Under review on IEEE Internet of Things Journal (IEEE IOTJ)
arXiv:1805.01831 [cs.RO]

   A Sub-mW IoT-Endnode for Always-On Visual Monitoring and Smart Triggering Image Processing
Manuele Rusci, Davide Rossi, Elisabetta Farella and Luca Benini
IEEE Internet of Things Journal, 4 (5): 1284-1295, New York, NY: IEEE, 2017.
DOI: 10.1109/JIOT.2017.2731301

   Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection Application (ExG)
Fabio Montagna, Simone Benatti, Davide Rossi
Journal of Low Power Electronics and Applications, 7 (2): 16, Basel: MDPI, 2017.
DOI: 10.3390/jlpea7020016

   A machine learning approach for automated wide-range frequency tagging analysis in embedded neuromonitoring systems Application (ExG)
Fabio Montagna, Marco Buiatti, Simone Benatti, Davide Rossi, Elisabetta Farella, Luca Benini
Methods, 129: 96 - 107, Amsterdam, Elsevier BV, 2017.
DOI: 10.1016/j.ymeth.2017.06.019

  A Self-Aware Architecture for PVT Compensation and Power Nap in Near-Threshold Processors
Davide Rossi, Igor Loi, Antonio Pullini, Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini and Philippe Flatresse
IEEE Design & Test, 34 (6): 46-53, New York, NY: IEEE, 2017.
DOI: 10.1109/MDAT.2017.2750907

  An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics Machine Learning
Francesco Conti, Robert Schilling, Pasquale D. Schiavone, Antonio Pullini, Davide Rossi, Frank K. Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard and Luca Benini
IEEE Transactions on Circuits and Systems I, Regular Papers, 64 (9): 2481-2494, New York, NY: IEEE, 2017.
DOI: 10.1109/TCSI.2017.2698019

  Lightweight Virtual Memory Support for Zero-Copy Sharing of Pointer-Rich Data Structures in Heterogeneous Embedded SoCs Programming
Pirmin Vogel, Andrea Marongiu, Luca Benini
IEEE Transactions on Parallel and Distributed Systems 28 (7): 1947 - 1959, New York, NY: IEEE, 2017.
DOI: 10.1109/TPDS.2016.2645219

  Efficient Virtual Memory Sharing via On-Accelerator Page Table Walking in Heterogeneous Embedded SoCs Programming
Pirmin Vogel, Andreas Kurth, Johannes Weinbuch, Andrea Marongiu, Luca Benini
ACM Transactions on Embedded Computing Systems 16 (5s): 154:1 - 154:19, New York, NY: ACM, 2017.
DOI: 10.1145/3126560

  Enabling Zero-Copy OpenMP Offloading on the PULP Many-Core Accelerator Programming
Alessandro Capotondi, Andrea Marongiu
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES '17), 68-71, New York, NY: ACM, 2017.
DOI: 10.1145/3078659.3079071

  Scalable EEG seizure detection on an ultra low power multi-core architecture Application (ExG)
Simone Benatti, Fabio Montagna, Davide Rossi and Luca Benini
2016 IEEE Biomedical Circuits and Systems Conference (BioCAS 2016), 86-89, Piscataway, NJ: IEEE, 2016.
DOI: 10.1109/BioCAS.2016.7833731

  193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beigný, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse and Luca Benini
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2016 (IEEE COOL CHIPS XIX), 7503670, Piscataway, NJ: IEEE, 2016.
DOI: 10.1109/CoolChips.2016.7503670

  An Event-Driven Ultra-Low-Power Smart Visual Sensor Application
Manuele Rusci, Davide Rossi, Michela Lecca, Massimo Gottardi, Elisabetta Farella, Luca Benini
IEEE Sensors Journal, 16 (13): 5344-5353, Piscataway, NJ: IEEE, 2016.
DOI: 10.1109/JSEN.2016.2556421

  A 65nm CMOS 6.4-to-29.2 pJ/FLOP@ 0.8 V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster
Michael Gautschi, Michael Schaffner, Frank Kagan Gürkaynak, Luca Benini
2016 IEEE International Solid-State Circuits Conference (ISSCC), 82-83 : San Francisco, CA: IEEE 2016.
DOI: 10.1109/ISSCC.2016.7417917

  High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme
Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank Kagan Gürkaynak, Luca Benini
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1387-1392, Piscataway, NJ: IEEE, 2016.
DOI: 10.3850/9783981537079_0174

  Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms Programming
Francesco Conti, Daniele Palossi, Andrea Marongiu, Davide Rossi and Luca Benini
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1201-1206, Piscataway, NJ: IEEE, 2016.
DOI: 10.3850/9783981537079_0626

  A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision Machine Learning Application
Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi and Luca Benini
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2910-2910, Piscataway, NJ: IEEE, 2016.
DOI: 10.1109/ISCAS.2016.7539213

  PULP: A Parallel Ultra Low Power platform for next generation IoT Applications
Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
2015 IEEE Hot Chips 27 Symposium (HCS), 7477325, New York, NY: IEEE, 2016.
DOI: 10.1109/HOTCHIPS.2015.7477325

  A 60 GOPS/W, -1.8V to 0.9V body bias ULP cluster in 28nm UTBB FD-SOI technology
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gürkaynak, Andrea Bartolini, Philippe Flatresse and Luca Benini
Solid-State Electronics, 117: 170-184, Kidlington: Elsevier Science, 2016.
DOI: 10.1016/j.sse.2015.11.015

  Power, Area, and Performance Optimization of Standard Cell Memory Arrays through Controlled Placement
Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
ACM Transactions on Design Automation of Electronic Systems (TODAES), 21 (4): 59:1-59:25, New York, NY: ACM, 2016.
DOI: 10.1145/2890498

  Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters
Igor Loi, Davide Rossi, Germain Haugou, Michael Gautschi and Luca Benini
Proceedings of the 12th ACM International Conference on Computing Frontiers, 64:1-64:8, New York, NY: ACM, 2015.
DOI: 10.1145/2742854.2747288

  Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI
Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
The 20th Asia and South Pacific Design Automation Conference, 81-86, Piscataway, NJ: IEEE, 2015.
DOI: 10.1109/ASPDAC.2015.7058985

  Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores
Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta
2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 25-30: IEEE, 2015.
DOI: 10.1109/VLSI-SoC.2015.7314386

  A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
Davide Rossi, Antonio Pullini, Michael Gautschi, Igor Loi, Frank K. Gürkaynak, Philippe Flatresse and Luca Benini
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 1-3, Piscataway, NJ: IEEE, 2015.
DOI: 10.1109/S3S.2015.7333483

  A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters Machine Learning
Francesco Conti, Luca Benini
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 683-688, Piscataway, NJ: IEEE, 2015.
DOI: 10.7873/DATE.2015.0404

  Lightweight Virtual Memory Support for Many-Core Accelerators in Heterogeneous Embedded SoCs Programming
Pirmin Vogel, Andrea Marongiu, Luca Benini
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES '15), 45-54, Piscataway, NJ: IEEE, 2015.
DOI: 10.1109/CODESISSS.2015.7331367

  Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory
Michael Gautschi, Davide Rossi and Luca Benini
Proceedings of the 24th edition of the great lakes symposium on VLSI, 87-88, New York, NY: ACM, 2014
DOI: 10.1145/2591513.2591569

  Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters
Davide Rossi, Igor Loi, Germain Haugou and Luca Benini
Proceedings of the 11th ACM Conference on Computing Frontiers, 15, Piscataway, NJ: IEEE, 2014.
DOI: 10.1145/2597917.2597922

  Energy-efficient vision on the PULP platform for ultra-low power parallel computing
Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi and Luca Benini
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, Piscataway, NJ: IEEE, 2014.
DOI: 10.1109/SiPS.2014.6986099

  Energy efficient parallel computing on the PULP platform with support for OpenMP Programming
Davide Rossi, Igor Loi, Francesco Conti, Giuseppe Tagliavini, Antonio Pullini and Andrea Marongiu
IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), 2014 : 3 - 5 Dec. 2014, Eilat, Piscataway,NJ: IEEE, 2014.
DOI: 10.1109/EEEI.2014.7005803