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Full Version: several questions about Pulpissimo SoC platform
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Hi,
I've already run "Hello" case successfully with Xcelium, now I have some further questions:
1. In readme I see it says "Either the RI5CY core or the Ibex one as main core". So by default, if I've built everything following readme, which core is used in the Soc?
2. In ARM cores, there is usually a program counter (PC) register, so that users can simply know where the issue happens (with disassembly code). Is there the similar register in Pulpissimo?
3. I see ./sim/boot/boot_code.cde is loaded in boot_rom. Is this boot_code.cde necessary for all the cases? Via the waveform of "Hello" case, I see something is read from boot_rom, but i'm not sure if the boot code is really used or not. What does the boot code do? Initialize the SoC? If I put my executable in SPI flash, can I still reuse the boot code before jumping to SPI content?
1. RI5CY is the default
2. the signal named pc_id is the pc value at decode stage, this is most likely what you are looking for. If you use questasim, you can source the software_debug.tcl script, it will show register values, pc and disassembly in the waveform viewer
3. the boot code can be found here https://github.com/pulp-platform/boot-co...oot_code.c. Is is there to support SPI and JTAG booting which can be select by driving bootsel accordingly. So the bootcode will read the bootsel bit and either start reading from spi flash dumping into l2 and then jump to the entry point or just busy loop (or wfi) until the debug module takes control of the execution.
(04-07-2020, 06:20 AM)bluewww Wrote: [ -> ]1. RI5CY is the default
2. the signal named pc_id is the pc value at decode stage, this is most likely what you are looking for. If you use questasim, you can source the software_debug.tcl script, it will show register values, pc and disassembly in the waveform viewer
3. the boot code can be found here https://github.com/pulp-platform/boot-co...oot_code.c. Is is there to support SPI and JTAG booting which can be select by driving bootsel accordingly. So the bootcode will read the bootsel bit and either start reading from spi flash dumping into l2 and then jump to the entry point or just busy loop (or wfi) until the debug module takes control of the execution.

Thank you so much!
2. I find a signal "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.riscv_tracer_i.pc[31:0]" whose value is equivalent to pc_id, and I've confirmed it's aligned with disassembly
3. Just double check with you --- do you mean first I assign the pin "pad_bootsel" to 1'b0 (for spi flash), then boot code will read the value of this signal and decide where to jump?
Yes the the pad_bootsel. 1'b1 for JTAG, 1'b0 for STANDALONE (spi flash).