Unable to compile and run applications on Zedboard with Pulpissimo

[victorgervasio]

Hello,

I'm a beginner and for the past two weeks I've been trying to compile applications on Zedboard (Pulpissimo), but I was unable to execute the "make" command for the pulp-sdk without getting errors.

I've tried to build the pulp-sdk commit 3256fe7, since newer commits apparently don't support board_targets anymore and tried to build the pulp-sdk on both Ubuntu 16.04 (fresh distribution, on VM using VirtualBox, as recommended in pulp-sdk's git commit id 3256fe7 Readme) and Ubuntu 18.04 (fresh distribution, on VM using VirtualBox, after changing my default gcc, gcc-7, to gcc-5, as recommended in pulp-sdk's git commit id 3256fe7 Readme an with conda environment with python3.5 and correspondent version pip installed).

I've successfully built the pulp-riscv-gnu-toolchain (the toolchain's version referenced by the pulp-sdk's git commit id 3256fe7 Readme) and I've also been able to generate and flash the Pulpissimo bitstream to the Zedboard. However, I can't make the SDK work, which I assume is the only supported way to compile applications on the FPGA with Pulpissimo.

On Ubuntu 16.04, this is the error message that keeps showing after "make all" for pulp-sdk (on root shell, since it's installation path is /opt/riscv, which lacks writing permissions unless I'm root):

Traceback (most recent call last):
  File "./pulp-tools/bin/plpbuild", line 3, in <module>
    import plptools as plp
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plptools.py", line 23, in <module>
    import plptools_builder
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plptools_builder.py", line 19, in <module>
    from twisted.internet import protocol, reactor, endpoints
  File "/usr/local/lib/python3.5/dist-packages/twisted/__init__.py", line 10, in <module>
    from twisted._version import __version__ as version
  File "/usr/local/lib/python3.5/dist-packages/twisted/_version.py", line 8, in <module>
    from incremental import Version
  File "/usr/local/lib/python3.5/dist-packages/incremental/__init__.py", line 469
    opt_in: bool
          ^
SyntaxError: invalid syntax
Makefile:6: recipe for target 'all' failed
make: *** [all] Error 1

On Ubuntu 18.04, this is the error message that keeps showing after "make all" for pulp-sdk (also on root shell):

make[2]: /opt/riscv/pulp-sdk/pkg/pulp_riscv_gcc/1.0.13/bin/riscv32-unknown-elf-gcc: Command not found
/opt/riscv/pulp-sdk/build/sdk/pulp-rt/pulpissimo/__rules.mk:58: recipe for target '/opt/riscv/pulp-sdk/build/sdk/pulp-rt/pulpissimo/rt/fc/kernel/init.o' failed
make[2]: *** [/opt/riscv/pulp-sdk/build/sdk/pulp-rt/pulpissimo/rt/fc/kernel/init.o] Error 127
make[2]: Leaving directory '/opt/riscv/pulp-sdk/runtime/pulp-rt'
Makefile:115: recipe for target 'build_all' failed
make[1]: *** [build_all] Error 2
make[1]: Leaving directory '/opt/riscv/pulp-sdk/runtime/pulp-rt'
Reached EOF with exit status 2
FATAL ERROR: the command 'build' has failed
Makefile:6: recipe for target 'all' failed
make: *** [all] Error 255

I'd like to know if it is still possible nowadays to compile and run applications for the Zedboard with Pulpissimo and, if so, I'd like some advice on what I'm doing wrong.

Thanks in advance!

[kgf]

The first one seems to be some sort of Python package incompatibility, the second one is that the tool chain (gcc) is not in the address you have specified.

I would not take random commits, but the tagged releases if you want less issues.

There is a very recent step by step tutorial by Ievgen Korotkyi from Kyiv School of Economics:
https://dspdev.io/en/posts/pulp-sdk-examples/

It should get you started,
Hope that helps

[victorgervasio]

Hi, thanks for the fast and helpful reply!

Following the step by step tutorial I have been able to simulate the "Hello !" example on QuestaSim! However, compiling and running applications on the FPGA (Zedboard) with Pulpissimo is a requirement for an undergraduate research project which I am currently taking part of, so I need to go further. In the step by step tutorial, the use Pulpissimo's v7.0.0 release is instructed (git checkout v7.0.0), since that is the release "which supports working with pulp-sdk", but over at https://github.com/pulp-platform/pulpissimo/releases/tag/v7.0.0 , it is stated that support for Xilinx Zedboard is removed, due to Zedboard's lack of space to fit the Pulpissimo design. It is also said that "the bitstream generation flow will fail due to insuffienct LUTs available", statement which I guess I have empirically verified.

Code:

53 Infos, 54 Warnings, 6 Critical Warnings and 3 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Mon Mar 24 15:49:00 2025...
[Mon Mar 24 15:49:01 2025] impl_1 finished
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Mar 24 15:49:01 2025...
Makefile:14: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/victor/pulp_box/pulpissimo/fpga/pulpissimo-zedboard'
Makefile:53: recipe for target 'zedboard' failed
make: *** [zedboard] Error 2

Because of that, I have tried to use Pulpissimo's v6.0.0 release, since it is my goal to work with the Zedboard. I have, then, been able to build pulp-sdk, generate the bitstream for Pulpissimo and flash it to the Zedboard without errors. However, I am unable to set and use OpenOCD as instructed on Pulpissimo's v6.0.0 ReadMe file. I am citing my commands and the error that I can't still make sense of:

1. cd pulpissimo
   
2. git checkout v6.0.0
   
3. make build-pulp-sdk
   
4. source env/pulpissimo.sh
   
5. make checkout (after that, I modified the rtl_vopt.tcl as suggested on the guide just regarding QuestaSim compatibility)
   
6. make build
   
7. cd ~/pulp_box/pulpissimo
   
8. ./update-ips
   
9. cd fpga
   
10. make zedboard (then, flashed the bitstream to the FPGA without erros)
    
11. cd ../pulp-sdk
    
12. source configs/pulpissimo.sh
    
13. source configs/fpgas/pulpissimo/genesys2.sh
    
14. make clean all (after that, I have installed all required dependencies for OpenOCD compilation)
    
15. source sourceme.sh && ./pulp-tools/bin/plpbuild checkout build --p openocd --stdout
    
16. export OPENOCD=~/pulp_box/pulpissimo/pulp-sdk/pkg/openocd/1.0
    
17. $OPENOCD/bin/openocd -f ~/pulp_box/pulpissimo/fpga/pulpissimo-zedboard/openocd-zedboard-hs2.cfg 
    

That last command gives me the following error:

Code:

Open On-Chip Debugger 0.10.0+dev-00615-g53a17c1bb (2025-03-24-17:22)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Warn : JTAG tap: riscv.unknown0       UNEXPECTED: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Error: JTAG tap: riscv.unknown0  expected 1 of 1: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Warn : JTAG tap: riscv.cpu       UNEXPECTED: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Error: JTAG tap: riscv.cpu  expected 1 of 1: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Error: Trying to use configured scan chain anyway...
Error: riscv.cpu: IR capture error; saw 0x03 not 0x01
Warn : Bypassing JTAG setup events due to errors
openocd: src/target/riscv/riscv.c:2366: riscv_xlen_of_hart: Assertion `r->xlen[hartid] != -1' failed.
Aborted (core dumped)

Then, I have tried to use Pulpissimo v7.0.0 to compile OpenOCD (but doing git checkout v7.0.0 this time) and got the same error:

Code:

Open On-Chip Debugger 0.10.0+dev-00615-g2785f0f5c (2025-03-24-18:06)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Warn : JTAG tap: riscv.unknown0       UNEXPECTED: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Error: JTAG tap: riscv.unknown0  expected 1 of 1: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Warn : JTAG tap: riscv.cpu       UNEXPECTED: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Error: JTAG tap: riscv.cpu  expected 1 of 1: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Error: Trying to use configured scan chain anyway...
Error: riscv.cpu: IR capture error; saw 0x03 not 0x01
Warn : Bypassing JTAG setup events due to errors
openocd: src/target/riscv/riscv.c:2366: riscv_xlen_of_hart: Assertion `r->xlen[hartid] != -1' failed.
Aborted (core dumped)

I was wondering if you could enlighten me regarding this problem. Maybe there is some misconception on my behalf about the process to compile OpenOCD, but I am not sure if it is possible to use it to load binaries into Pulpissimo v6.0.0 on the Zedboard.                                               
 Thank you again for your attention!