Hi, 

I have a Pulpissimo chip we sent to a foundry to manufacture. It was synthesized based on pulpissimo releases v7.0.0. We have managed to run a couple of tests on 20MHz.
The problem is when trying to boot from SPI by forcing '00' on bootsel, the spi pads does not respond. We have tried keeping the jtag connector on or disconnecting it from the board. 

Also, on Questasim, when trying to boot from a mode different than the specified from the RTL, e.g., STANDALONE and SPI_FLASH on tb_pulp.sv and forcing '00' on bootsel in the simulation, the transcript posts Branch decision X, when trying to load the 2nd page. The flash content is erased because I did not call the simulation with the arguments to load the program on the flash, but still it should get the error after loading the program and trying to run it, right?

I appreciate if there are any suggestions on how we can make the boot work.

Thanks in advance, Ivan.

I am using the machine and user mode on the pulp (CV32E40P). As far as I understand I need to set UTVEC and MTVEC to the corresponding locations of interrupt vector table. I also registered a handler for ex timer (machine mode handler + user mode handler individiually) and enabled the timer. Then I can enable the interrupts in MSTATUS or USTATUS. 

My observation is: 
* when beeing in user mode => interrupts are pushed to UTVEC and handled in user mode
* when beeing in machine mode => interrupts are pushed to MTVEC and handled in machine mode

However I was expecting some kind of configuration where all interrupts are preferably handled by machine mode (always) => where and how can I configure this? (I expected some implementation of medeleg and mideleg, but this doesnt seem to exist?)

any hints are welcome. thank you in advance.


***update***

if I leave the user interrupt in USTATUS disabled, then in both modes the handler of machine mode will be triggered. however as the user can enable the user interrupt in USTATUS, I would still expect the machine mode handler to be triggered with higher priority - thus should be triggered first => but that is not happening.

***hints***

Quote:An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and © if register mideleg exists, bit i is not set in mideleg.

Hi, Is it possible to compile and run CNNs on FPGA (pulp)? If so, could you direct me to a guide or tutorial on how to achieve this? This information is crucial for my work.

Hi, I am trying to deploy a custom model on the PULP platform. So far, I have successfully quantized the custom model and generated the ".onnx" file through the NEMO. However, while generating the network through the "network_generate.py" file under the DORY, I get an error: "out_layer0.txt not found". How can I get the required ".txt" files such as "input.txt",  "out_layer0.txt", "out_layer1.txt" and so on? Also, I would like to know if the ".json" file containing information about the model parameters can be generated automatically. Or do I have to fill it in manually? I would be very grateful for your reply!

I have built the docker and cloned the snitch_cluster repo in /repo.
And then in the target/snitch_cluster, I use the command make bin/snitch_cluster.vlt

For which I get:
work-vlt/Vtestharness.h:11:10: fatal error: verilated_heavy.h: No such file or directory


What am I doing wrong here?


Commands I have used:
   

1. To build docker:
   
   Code:

   sudo docker build -t ghcr.io/pulp-platform/snitch_cluster:main -f util/container/Dockerfile .
   2.  In the snitch_cluster root: docker run -it -v $REPO_TOP:/repo -w /repo ghcr.io/pulp-platform/snitch_cluster:main
   3.  In /repo of docker: git clone https://github.com/pulp-platform/snitch_cluster.git --recurse-submodules
   4.  In /repo/snitch_cluster/target/snitch_cluster: make bin/snitch_cluster.vlt
   
   
   

When trying to run the setup for RTL simulation of the HERO Project's accelerator through synthesis, two modules are not synthesizable, namely axi_sim_mem and apb_stdout. Are there preexisting versions of these two modules that will pass synthesis, or would I just have to try and make them synthesizable while trying to maintain the default functionality as much as possible? TIA

Hi,
I tried to connect to pulpissimo via jtag using openocd, but always get this error:
   
I tried on 2 different fpgas: zedboard and zcu104 and get the same error. This is my openocd config file:
   
I have been struggle with this error for weeks and really need help :<

Hello everyone,

Im currently doing a research for a future proyect about RISC V based core IPs,  chips, devboards fully designed and manufactured in Europe that are being commercialized right now. Preferable if the devboard counts with multiple communication protocols, no FPGAs, less 25W consumption, no SoC.
If in development I  would also appreciate the information. I know SiFive is selling european designed and manufactured RISC V dev boards, but, the RISC V chips themselfs are manufactured in China.

Thank you in advance for the assistance.

Hi, I am Jay Huang, a Verification Engineer at Taiwan Electronic System Design Automation (TESDA). Currently, we are utilizing your open-source SOC, PULPino, to develop our verification tools.

During the course of our SOC implementation, we have encountered some challenges related to the PULPino Boot ROM, prompting us to seek clarification on certain aspects. According to the datasheet Memory Map, the Boot ROM's address range is specified as 0x0008_0000 to 0x0008_0200.

In an attempt to integrate this information into our testbench, I observed that when attempting to read from this address range, no data was retrieved. After further investigation, it was determined that the Boot ROM is, in fact, located immediately following the Instruction Memory, rather than at the specified address.

I would like to ask if it is correct to set the start address of the Boot ROM at 0x0000_8000 if the Instruction Memory is configured as 32KB?
If this configuration is indeed correct, I am curious as to why the Boot ROM's address in the datasheet is documented as 0x0008_0000 to 0x0008_0200.

Your insights and guidance on this matter would be immensely valuable to us in resolving the issues we are currently facing. Thank you for your time and attention to this inquiry.

Hi, 

I was trying to implement a solution to add AES and maybe other crypto extensions in Pulpissimo. I tried to change the core to a variant of the RI5CY, CV32E40S that support some of that extensions. 
When I run a test that worked on the original core, the JTAG halts the core in the simulation. 

I was wondering if there is something to do with the SDK (by the way, i'm using this platform for a while so i'm still using releases 7.0 and pulp-sdk) or the toolchain to make it work, or is it just a problem in the connection of the core. There are quite a few more ports so, just to start trying, I left some of the ports that seemed optional from the documentation. 

Thanks in advance.