Welcome, Guest
You have to register before you can post on our site.

Username
  

Password
  





Search Forums

(Advanced Search)

Forum Statistics
» Members: 157
» Latest member: rugbyworldc
» Forum threads: 62
» Forum posts: 212

Full Statistics

Latest Threads
Pulpissimo bitstream gene...
Forum: PULP General questions
Last Post: meggiman
Yesterday, 11:14 AM
» Replies: 12
» Views: 402
Error on Macro 'DMI_JTAG_...
Forum: PULP General questions
Last Post: mapletree
06-21-2019, 05:09 PM
» Replies: 0
» Views: 190
Integrating NVDLA with PU...
Forum: PULP General questions
Last Post: AhmedZaky
06-13-2019, 04:17 PM
» Replies: 0
» Views: 248
which spike version for r...
Forum: PULP General questions
Last Post: etayke
06-11-2019, 02:52 PM
» Replies: 0
» Views: 208
xilinx memories in pulpis...
Forum: PULP General questions
Last Post: meggiman
06-10-2019, 09:02 AM
» Replies: 1
» Views: 330
Pulpissimo L2 memory acce...
Forum: PULP General questions
Last Post: skor
06-06-2019, 06:26 AM
» Replies: 4
» Views: 713
Porting Ariane to KC705
Forum: PULP General questions
Last Post: AnonymousWeasel
06-05-2019, 09:05 AM
» Replies: 1
» Views: 403
FPGA build
Forum: PULP General questions
Last Post: Akim
06-05-2019, 07:34 AM
» Replies: 2
» Views: 558
how to add a new ISR into...
Forum: PULP General questions
Last Post: Tommy Hsu
06-05-2019, 03:13 AM
» Replies: 0
» Views: 239
Using HAL headers in HERO...
Forum: PULP General questions
Last Post: tmilkovic
06-03-2019, 11:46 AM
» Replies: 0
» Views: 251

 
  Pulpissimo bitstream generation.
Posted by: naprpo - 06-27-2019, 12:43 PM - Forum: PULP General questions - Replies (12)

Hello,

I got the following errors during bitstream generation for genesys2 board.

Code:
open_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 7121.617 ; gain = 0.000 ; free physical = 3356 ; free virtual = 8201
# exec mkdir -p reports/
# exec rm -rf reports/*
# check_timing                                                              -file reports/${project}.check_timing.rpt
# report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/${project}.timing_WORST_100.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack.
# report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/${project}.timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group.
# report_utilization -hierarchical                                          -file reports/${project}.utilization.rpt
INFO: [Common 17-206] Exiting Vivado at Thu Jun 27 15:20:28 2019...
make[1]: Leaving directory `********/pulpissimo/fpga/pulpissimo-genesys2'
cp pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit
cp: cannot stat ‘pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit’: No such file or directory
make: *** [genesys2] Error 1

Even the console shows error, the .bit file is generated. I loaded the .bit file to genesys2 board and try to read and write in the memory with the plpbridge. Which didn't work.

Code:
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent write --addr=0x1c000000 --size=32 --value=0x12345678
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent read --addr=0x1c000000 --size=32
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
ft2232: did not get a start bit from the AXI module in 1s
1c000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1c000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00



I also tried to communicate with RISC-V debug module with openOCD. Got the following output.

Code:
Open On-Chip Debugger 0.10.0+dev-00619-g91faf1a (2019-06-27-13:52)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
  TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 32 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info :  hart 5: currently disabled
Info :  hart 6: currently disabled
Info :  hart 7: currently disabled
Info :  hart 8: currently disabled
Info :  hart 9: currently disabled
Info :  hart 10: currently disabled
Info :  hart 11: currently disabled
Info :  hart 12: currently disabled
Info :  hart 13: currently disabled
Info :  hart 14: currently disabled
Info :  hart 15: currently disabled
Info :  hart 16: currently disabled
Info :  hart 17: currently disabled
Info :  hart 18: currently disabled
Info :  hart 19: currently disabled
Info :  hart 20: currently disabled
Info :  hart 21: currently disabled
Info :  hart 22: currently disabled
Info :  hart 23: currently disabled
Info :  hart 24: currently disabled
Info :  hart 25: currently disabled
Info :  hart 26: currently disabled
Info :  hart 27: currently disabled
Info :  hart 28: currently disabled
Info :  hart 29: currently disabled
Info :  hart 30: currently disabled
Info :  hart 31: currently disabled
openocd: src/target/riscv/riscv.c:2522: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed.
Aborted (core dumped)
Could you please point out what am i missing here ?
Regards,
naprpo

Print this item

  Error on Macro 'DMI_JTAG_IDCODE is not defined when built pulp RTL simulation pfm
Posted by: mapletree - 06-21-2019, 05:09 PM - Forum: PULP General questions - No Replies

Hi,
I am trying to build the pulp RTL simulaltion platform following the instructions provided on the github page:
https://github.com/pulp-platform/pulp.

At the steps:

Code:
source setup/vsim.sh
cd sim/
make clean lib build opt

I got the following error:
** Error: ../ips/pulp_soc/rtl/pulp_soc/pulp_soc.sv(800): (vlog-2163) Macro 'DMI_JTAG_IDCODE is not defined.

Does anyone ever get the same problem? is there a solution to fix it?

Thanks!

I replaced the pulp_soc_defines.sv with the one coming with pulpissimo platform that includes the definition of the DMI_JTAG_IDCODE, then the error is gone.

Print this item

  Integrating NVDLA with PULPissimo
Posted by: AhmedZaky - 06-13-2019, 04:17 PM - Forum: PULP General questions - No Replies

Hey All, 

I am trying to integrate NVDLA accelerator into PULPissimo platform through AXI4 interface. Has anyone done it before ? What's the limitations in terms of both hardware and software integration ? 

Thanks !

Print this item

  which spike version for ri5cy?
Posted by: etayke - 06-11-2019, 02:52 PM - Forum: PULP General questions - No Replies

Hi,

we are using the ri5cy core, pulpinov1 branch, and wanted to understand which spike (isa simulator) repository should be taken.

i have found this:
https://github.com/pulp-platform/riscv-isa-sim
1. is there a specific branch matching the pulpinov1 design version
2. does it have any specific ri5cy compliance, special flags or any other?
3. am i supposed to take any patch to make it match ri5scy, as the toolchain?

for the toolchain, we are taking this :
https://github.com/pulp-platform/ri5cy_gnu_toolchain
which i understand patches the original pulp platform toolchain to match the ri5cy.

would appreciate any help on this topic.

thanks,
Itay K.

Print this item

  xilinx memories in pulpissimo L2
Posted by: skor - 06-10-2019, 06:47 AM - Forum: PULP General questions - Replies (1)

Hi,

In Pulpissimo in l2_ram_multi_bank.sv there is hooks for xilinx memories:
`ifdef PULP_FPGA_EMUL

      logic [NB_BANKS-1:0][7:0]   wea;

      genvar                      i,j;
      generate
         for(i=0; i<NB_BANKS; i++)
         begin : CUTS
            for(j=0; j<8; j++)
            assign wea[i][j] = ~mem_slave[i].csn & ~mem_slave[i].wen & mem_slave[i].be[j];

            xilinx_l2_mem_8192x64 l2_mem_i (
               .clka  ( clk_i                                ),
               .rsta  ( ~rst_ni                              ),
               .ena   ( ~mem_slave[i].csn                    ),
               .wea   ( wea[i]                               ),
               .addra ( mem_slave[i].add[MEM_ADDR_WIDTH-1:0] ),
               .dina  ( mem_slave[i].wdata                   ),
               .douta ( mem_slave[i].rdata                   )
            );
         end
      endgenerate

Have you tested this is working?

Regards, skor

Print this item

  how to add a new ISR into interrupt vector table
Posted by: Tommy Hsu - 06-05-2019, 03:13 AM - Forum: PULP General questions - No Replies

Hi, we are developing a RISC-V project which need to add some ISRs for peripheral hardware, is there any tutorial or example to reference??

thanks!!

Print this item

  Using HAL headers in HERO project
Posted by: tmilkovic - 06-03-2019, 11:46 AM - Forum: PULP General questions - No Replies

Hi!

I would like to use eu_evt_maskWaitAndClr() HAL function to put the RISC-V core to sleep until my HWPE signals an event (job done). I am using HERO-SDK.
I tried including eu_v3.h header in my code (between #pragma omp declare target and #pragma omp end declare target), but compiler gives me fatal error: eu_v3.h: No such file or directory. Is it even posible to use headers from pulp-sdk inside hero-sdk project?

Best regards,
Tomislav

Print this item

  How to simulate the bootloader with flash S25fs256s verilog model for pulpino?
Posted by: zhouqiang - 05-25-2019, 04:52 AM - Forum: PULP General questions - No Replies

Hi,
  I want to try to simluate the bootloader with flash S25fs256s,  so that I can simluate with the  flash. I have found the verilog model of S25fs256s according to https://github.com/pulp-platform/pulpiss.../spi_flash, and I have instantiated the generic pad for each signal coming from my SPI model according to https://github.com/pulp-platform/pulpino/issues/16, and in order to test boot_code, I changed MEMLOAD on https://github.com/pulp-platform/pulpino/blob/master/vsim/tcl_files/run.tcl, from PRELOAD to STANDALONE.  I instantiated the flash module in the pulpion_top file, but when I run "make testSPIMASTER.vsim" or "make helloworld.vsim" ,  but still encounter the error  "RX string: ERROR: Spansion SPI flash not found” ,can someone tell me how to deal with the error? How can make it to find the Spanison SPI flash ?

Print this item

  Pulpissimo synthesis error
Posted by: MikkeN - 05-23-2019, 11:25 AM - Forum: PULP General questions - No Replies

Hi,

I got following error when synthesising (dc_shell L2016-03) Pulpissimo:


Information: Building the design 'pulp_soc' instantiated from design 'soc_domain_0_1_32_64_32_6_4_6_8_4_8_8' with
        the parameters "CORE_TYPE=0,USE_FPU=1,AXI_ADDR_WIDTH=32,AXI_DATA_IN_WIDTH=64,AXI_DATA_OUT_WIDTH=32,AXI_ID_IN_WIDTH=6,AXI_ID_OUT_WIDTH=4,AXI_USER_WIDTH=6,EVNT_WIDTH=8,BUFFER_WIDTH=8". (HDL-193)
Error:  ../pulpissimo/ips/pulp_soc/rtl/pulp_soc/pulp_soc.sv:269: Syntax error at or near token 'FC_Core_MHARTID': arrays do not have named members. (VER-294)
*** Presto compilation terminated with 2 errors. ***

MikkeN

Print this item

  Porting Ariane to KC705
Posted by: AnonymousWeasel - 05-22-2019, 04:09 PM - Forum: PULP General questions - Replies (1)

Hello,

I'm currently porting the Ariane core to the KC705 board, as it is using the same FPGA as the Genesys II this should be a feasible task to do. So far I adapted the constraint file to match the KC705 board and also changed the part and board variables in the Makefile. The KC705 has different amounts of switches and LEDs so I reduced the number where necessary. Also the cpu_reset is inverted on the KC705. In the fpga/scripts/write_cfgmem.tcl I changed the SPI memory size parameter to 128 (as provided by the KC705).
The KC705 doesn't have an FTDI chip like the Genesys II. Therefore, the KC705 lacks the necessary configurable JTAG pins that are connected to the dmi_jtag module. For now I temporarily worked around that by wiring it up to a BSCANE2 module and hardwiring the trst to 1. In the future I plan on using a second JTAG that I connect to some GPIO pins to wire them up to the module.
I also built the ariane-sdk using the provided makefile and put it on an SD card.

The bitstream is sent to the KC705 just fine. I added some additional logic to to make sure the clock and reset are working by wiring them up to the LEDs, so this part seems to be just fine.

I checked the bootrom and according to the main.c in fpga/src/bootrom/src/ it is supposed to 'print_uart("Hello World!\r\n");' in the beginning of the bootrom. However, I don't receive this output (or any other) on my terminal.
I'm using the `screen /dev/ttyUSB0 115200` command from the github readme. I made sure to use the correct ttyUSB by dis- and reconnecting the separate UART cable on the KC705 while checking the /dev folder.

Are there any additional files/settings I need to adjust? Any idea how to get this to work or how to debug it?

Also:     During the `make fpga` an ariane.xpr vivado project file is created in the fpga folder. If I open this file it is empty, is this supposed to be the case? I wanted to add some ILA cores to further debug my issue, but without a working project this gets more tedious.
    
Thank you.

Edit: typos

Print this item