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Latest Threads |
CV32E40P/RI5CY Setup
Forum: PULP General questions
Last Post: e0960179@u.nus.edu
10-19-2024, 08:51 AM
» Replies: 0
» Views: 27
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How to get more detailed ...
Forum: PULP General questions
Last Post: YiZhi_W
10-17-2024, 08:06 AM
» Replies: 2
» Views: 99
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Which SDK to be used to c...
Forum: PULP General questions
Last Post: Tolido1
10-17-2024, 06:49 AM
» Replies: 1
» Views: 1,441
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Difference between RI5CY ...
Forum: PULP General questions
Last Post: eureka
09-27-2024, 06:17 AM
» Replies: 2
» Views: 261
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Extension documentation a...
Forum: PULP General questions
Last Post: kgf
08-14-2024, 05:04 PM
» Replies: 3
» Views: 797
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Synthesis of ARA Vector U...
Forum: PULP General questions
Last Post: Tanishq S
08-12-2024, 03:32 PM
» Replies: 2
» Views: 719
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how can i occur fmadd ins...
Forum: PULP General questions
Last Post: kgf
08-05-2024, 10:35 AM
» Replies: 1
» Views: 443
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i have some issue with si...
Forum: PULP General questions
Last Post: John Dowdell
08-04-2024, 07:16 AM
» Replies: 1
» Views: 620
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handling custom opcodes (...
Forum: PULP General questions
Last Post: Roogadget
07-25-2024, 01:18 PM
» Replies: 2
» Views: 655
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The pulpino verification
Forum: PULP General questions
Last Post: eureka
07-23-2024, 07:45 AM
» Replies: 2
» Views: 763
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CV32E40P/RI5CY Setup |
Posted by: e0960179@u.nus.edu - 10-19-2024, 08:51 AM - Forum: PULP General questions
- No Replies
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I am trying to use the CV32E40P/RI5CY core in a school project and am having a lot of trouble with the setup. This is the first time using an open source core so forgive me if some questions seem silly.
I added all the RTLs according to the manifest here
https://github.com/openhwgroup/cv32e40p/...fest.flist
However, when I try to synthesize the module on Xilinx Vivado (2023.2), I do not have enough IO pins. Referring to a paper (https://ieeexplore.ieee.org/document/10420491), I noted that there are more BRAMs in their synthesis so I am trying to wrap the inputs and outputs of the core in BRAMs, which seems like the correct direction. The problem is that my synthesis will optimize away my core module. I don't quite know how the BRAM method works.
Could anyone share about how they went about wrapping their inputs into BRAMs. For example, do you use 3 separate BRAMs for the instruction memory, Data Memory, and a last BRAM for any outputs that come from the core module? Also, how do you read the instruction memory? I don't see any Program Counter module in the RI5CY code.
Thank you
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How to get more detailed information about spatz |
Posted by: YiZhi_W - 10-16-2024, 06:12 AM - Forum: PULP General questions
- Replies (2)
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Hello! I'm a student studying RVV, and I'm very interested in spatz. I have obtained some materials about spatz, including papers, materials in the github repository, PPT on the official website, etc. however, I found that the documentation provided in the github repository is not comprehensive. The introduction in the papers also has some differences from the current hardware design.
I want to know the hardware design details of spatz and how spatz works with snitch. Could you please provide me with more detailed documentation? It will be very helpful to me.
Thank you very much!
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Synthesis of ARA Vector Unit |
Posted by: Tanishq S - 08-07-2024, 07:31 AM - Forum: PULP General questions
- Replies (2)
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Respected Moderator
I am currently working on synthesizing the ARA architecture along with the CVA6 processor. I have been trying to perform top-down mapping of the files by designating ara_soc.sv as the top module and consolidating all related files into a single .sv file for synthesis.
Unfortunately, I have encountered difficulties in achieving a successful synthesis in Cadence Genus. I am concerned that my approach might be flawed, and I am seeking guidance on how to resolve this issue.
Could you please provide me with some advice or best practices for synthesizing the ARA and CVA6 design in Cadence Genus or any other tool like Vivado or Synopsis DC? Any insights or suggestions on how to effectively manage the integration of these components would be greatly appreciated.
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how can i occur fmadd instruction? |
Posted by: sungyong - 07-29-2024, 08:08 AM - Forum: PULP General questions
- Replies (1)
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how can i occur the fmadd instruction with c code?
in regression examples
for (t=0; t<T; t++) {
for (i=2; i<N-1; i++) {
for (j=2; j<N-1; j++) {
b[i][j]= 0.2f*(a[i][j]+a[i][j-1]+a[i][1+j]+a[1+i][j]+a[i-1][j]);
printf("caculate finished # i=%d j=%d \n",i,j);
}
}
}
This example occurs fadd instrctions.
then, how can i occur fmadd instrctions? is there any special condition for it?
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The pulpino verification |
Posted by: eureka - 07-21-2024, 02:47 PM - Forum: PULP General questions
- Replies (2)
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Hello! I'm a student who is learning the riscv arch and the pulpino core, and I wonder how the team of pulpino verify the RV32IM instruction set and the custome instruction set, are your team use the official riscv-tests, or use riscv emulators like qemu or spike as ref, or build your own test sets.
Thank you very much!
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axi_xbar integration issue |
Posted by: malik775 - 07-12-2024, 05:46 PM - Forum: PULP General questions
- Replies (1)
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I am encountering an issue while using an AXI crossbar in my project, which has 2 slave ports and 1 master port. In the project, I have two DMAs accessing a single memory for read operations. I am using the PULP AXI_XBAR, and although it simulates, I am experiencing an error where the crossbar directs all request response data to one DMA. It correctly decodes read addresses from both DMAs but sends the response data to only one DMA. Can anyone guide me on this issue? Here is the crossbar configuration:
// AXI Configuration
localparam axi_pkg::xbar_cfg_t XbarCfg = '{
NoSlvPorts: 2,
NoMstPorts: 1,
MaxMstTrans: 20,
MaxSlvTrans: 10,
FallThrough: 1'b0,
LatencyMode: axi_pkg::CUT_ALL_AX,
PipelineStages: 2,
AxiIdWidthSlvPorts: 2,
AxiIdUsedSlvPorts: 2,
UniqueIds: 1'b0,
AxiAddrWidth: AddrWidth,
AxiDataWidth: DataWidth,
NoAddrRules: 1
};
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