I am trying to use the CV32E40P/RI5CY core in a school project and am having a lot of trouble with the setup. This is the first time using an open source core so forgive me if some questions seem silly. 

I added all the RTLs according to the manifest here 
https://github.com/openhwgroup/cv32e40p/...fest.flist

However, when I try to synthesize the module on Xilinx Vivado (2023.2), I do not have enough IO pins. Referring to a paper (https://ieeexplore.ieee.org/document/10420491), I noted that there are more BRAMs in their synthesis so I am trying to wrap the inputs and outputs of the core in BRAMs, which seems like the correct direction. The problem is that my synthesis will optimize away my core module. I don't quite know how the BRAM method works. 

Could anyone share about how they went about wrapping their inputs into BRAMs. For example, do you use 3 separate BRAMs for the instruction memory, Data Memory, and a last BRAM for any outputs that come from the core module? Also, how do you read the instruction memory? I don't see any Program Counter module in the RI5CY code. 

Thank you

Hello! I'm a student studying RVV, and I'm very interested in spatz. I have obtained some materials about spatz, including papers, materials in the github repository, PPT on the official website, etc. however, I found that the documentation provided in the github repository is not comprehensive. The introduction in the papers also has some differences from the current hardware design.
I want to know the hardware design details of spatz and how spatz works with snitch. Could you please provide me with more detailed documentation? It will be very helpful to me. 
Thank you very much!

Hello! I'm a student using pulp to do some research. I  formerly used the [pulpino] and this platform uses the [RI5CY] core. Now I'm using the [pulpissimo] and it uses the [CV32E40P] core.

I wonder if there is any difference between these two cores. because I found it says "32 bit 4-stage core CV32E40P (formerly RI5CY)", is this means that the difference between them is just name? Because I also compare the CV32E40P's github page and the RI5CY core cloned by the pulpino, there are many difference between files. For example, there is no [tracer] moudle in the [CV32E40P].

Since I want write the core ([RI5CY] or [CV32E40p]) to the FPGA and use it as a controller to control a NPU, I wonder is there a huge difference between these two cores in the PPA(performance, power, area)

Since I'm not a native English speaker, it may cause difficult when you reading my question, I'm very sorry about that!

Thank you very much!

Respected Moderator 


I am currently working on synthesizing the ARA architecture along with the CVA6 processor. I have been trying to perform top-down mapping of the files by designating ara_soc.sv as the top module and consolidating all related files into a single .sv file for synthesis.

Unfortunately, I have encountered difficulties in achieving a successful synthesis in Cadence Genus. I am concerned that my approach might be flawed, and I am seeking guidance on how to resolve this issue.

Could you please provide me with some advice or best practices for synthesizing the ARA and CVA6 design in Cadence Genus or any other tool like Vivado or Synopsis DC? Any insights or suggestions on how to effectively manage the integration of these components would be greatly appreciated.

Hello, when trying to ascertain the changes made to the pulp instructions for their core-v re-encoding (core-v.rst is the most detailed filed I've found) I found it was quite difficult to find what the original instructions actually were!
So far I've been basing my work on [1] and [2] and the file mentioned above. I've noticed the "pulp manuals" are mentioned at the beginning of [1], but the only thing that comes close to it is this datasheet, which appears to be in a somehow abandoned repository (still mentions the pulp riscv gnu toolchain in its readme), and only mentions some vector extension instructions.
For reference, I am looking for for information similar to the one in the core-v.rst file or the cv32e40p user's manual, and the information that can be extracted from [2].
Thank you!

how can i occur the fmadd instruction with c code?

in regression examples
      for (t=0; t<T; t++) {
        for (i=2; i<N-1; i++) {
          for (j=2; j<N-1; j++) {
            b[i][j]= 0.2f*(a[i][j]+a[i][j-1]+a[i][1+j]+a[1+i][j]+a[i-1][j]);
            printf("caculate finished # i=%d j=%d \n",i,j);
          }
        }
      }
This example occurs fadd instrctions. 
then, how can i occur fmadd instrctions? is there any special condition for it?

I'm doing some research to better understand how everything comes together when using pulpissimo.

I'm curious about the compiler and custom opcodes.

How and where does the compiler know how to handle these opcodes when compiling a program? Is it "Inline Assembly"?

I've found all the opcodes for the pulp0, pulp1..gap9...etc. Now I'm after looking for either "Machine Description Files", "target specific header files" or "Compiler Backend Code".

I'd like to add a custom opcode and have the compiler utilise that opcode in the future.

(I'm a complete compiler newbie.)

Thanks in advanced.

Hello! I'm a student who is learning the riscv arch and the pulpino core, and I wonder how the team of pulpino verify the RV32IM instruction set and the custome instruction set, are your team use the official riscv-tests, or use riscv emulators like qemu or spike as ref, or build your own test sets.

Thank you very much!

I'm looking for a block diagram of a stock pulpissimo. 

Showing the blocks from the packages list with ports, wires..etc. is this something seen at the vivido synthesis stage? 

Thanks in advance.

I am encountering an issue while using an AXI crossbar in my project, which has 2 slave ports and 1 master port. In the project, I have two DMAs accessing a single memory for read operations. I am using the PULP AXI_XBAR, and although it simulates, I am experiencing an error where the crossbar directs all request response data to one DMA. It correctly decodes read addresses from both DMAs but sends the response data to only one DMA. Can anyone guide me on this issue? Here is the crossbar configuration:
// AXI Configuration
localparam axi_pkg::xbar_cfg_t XbarCfg = '{
    NoSlvPorts: 2,
    NoMstPorts: 1,
    MaxMstTrans: 20,
    MaxSlvTrans: 10,
    FallThrough: 1'b0,
    LatencyMode: axi_pkg::CUT_ALL_AX,
    PipelineStages: 2,
    AxiIdWidthSlvPorts: 2,
    AxiIdUsedSlvPorts: 2,
    UniqueIds: 1'b0,
    AxiAddrWidth: AddrWidth,
    AxiDataWidth: DataWidth,
    NoAddrRules: 1
};