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Porting Ariane to KC705
Forum: PULP General questions
Last Post: AnonymousWeasel
35 minutes ago
» Replies: 0
» Views: 3
Lower number of cores on ...
Forum: PULP General questions
Last Post: lukamac
Yesterday, 09:13 AM
» Replies: 3
» Views: 172
Pulpissimo L2 memory acce...
Forum: PULP General questions
Last Post: skor
05-20-2019, 10:03 AM
» Replies: 3
» Views: 105
Pulpissimo Synthesis cont...
Forum: PULP General questions
Last Post: fconti
05-16-2019, 06:03 PM
» Replies: 3
» Views: 63
FPGA build
Forum: PULP General questions
Last Post: kgf
05-15-2019, 11:17 AM
» Replies: 1
» Views: 64
How to do post-synthesis ...
Forum: PULP General questions
Last Post: zhouqiang
05-10-2019, 02:05 AM
» Replies: 2
» Views: 86
[HERO] Userland applicati...
Forum: PULP General questions
Last Post: akurth
05-09-2019, 05:25 PM
» Replies: 1
» Views: 81
[PULP] Peripheral bus mem...
Forum: PULP General questions
Last Post: akurth
05-09-2019, 05:20 PM
» Replies: 1
» Views: 93
clock problem when writin...
Forum: PULP General questions
Last Post: zhouqiang
05-09-2019, 08:38 AM
» Replies: 2
» Views: 99
Pulpissimo synthesis
Forum: PULP General questions
Last Post: zhouqiang
05-08-2019, 12:30 PM
» Replies: 5
» Views: 132

  Porting Ariane to KC705
Posted by: AnonymousWeasel - 35 minutes ago - Forum: PULP General questions - No Replies


I'm currently porting the Ariane core to the KC705 board, as it is using the same FPGA as the Genesys II this should be a feasible task to do. So far I adapted the constraint file to match the KC705 board and also changed the part and board variables in the Makefile. The KC705 has different amounts of switches and LEDs so I reduced the number where necessary. Also the cpu_reset is inverted on the KC705. In the fpga/scripts/write_cfgmem.tcl I changed the SPI memory size parameter to 128 (as provided by the KC705).
The KC705 doesn't have an FTDI chip like the Genesys II. Therefore, the KC705 lacks the necessary configurable JTAG pins that are connected to the dmi_jtag module. For now I temporarily worked around that by wiring it up to a BSCANE2 module and hardwiring the trst to 1. In the future I plan on using a second JTAG that I connect to some GPIO pins to wire them up to the module.
I also built the ariane-sdk using the provided makefile and put it on an SD card.

The bitstream is sent to the KC705 just fine. I added some additional logic to to make sure the clock and reset are working by wiring them up to the LEDs, so this part seems to be just fine.

I checked the bootrom and according to the main.c in fpga/src/bootrom/src/ it is supposed to 'print_uart("Hello World!\r\n");' in the beginning of the bootrom. However, I don't receive this output (or any other) on my terminal.
I'm using the `screen /dev/ttyUSB0 115200` command from the github readme. I made sure to use the correct ttyUSB by dis- and reconnecting the separate UART cable on the KC705 while checking the /dev folder.

Are there additional files/settings I need adjust? Any idea how to this to work or how to debug it?

Also:     During the `make fpga` an ariane.xpr vivado project file is created in the fpga folder. If I open this file it is empty, is this supposed to be the case? I wanted to add some ILA cores to further debug my issue, but without a working project this gets more tedious.
Thank you.

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  Pulpissimo Synthesis content
Posted by: MikkeN - 05-16-2019, 10:42 AM - Forum: PULP General questions - Replies (3)


I have reviewed Pulpissimo code. There is couple of issues (I try to synthesize it):

1. In pulp_soc.sv (line 861) is instatiation of module jtag_tap_top. However this module is not found. Instead there is module tap_top,
should it be instantiated?

2. In soc_clk_rst_gen.sv there is three instatiations of gf22_FLL
Comment says that it is not supported by FPGA
Is this really synthesizable code?
There is comments regarding that it is behavioral coding.

Best Regards,

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  FPGA build
Posted by: Akim - 05-15-2019, 11:00 AM - Forum: PULP General questions - Replies (1)


I found that you have added more instructions (below) how to build and use virtual platform with Pulpissimo.
Thaks for that, I got virtual platform working and run Hello test on it.

Is there similar instructions for FPGA build? Is there somewhere build-fpga like build-gvsoc etc.?

"Building and using the virtual platform
Once the RTL platform is installed, the following commands can be executed to install and use the virtual platform:

git clone https://github.com/pulp-platform/pulp-builder.git
cd pulp-builder
git checkout b3b255b0f653fce950cf730972c8ad07b1be7bf0
source configs/pulpissimo.sh
source sdk-setup.sh
source configs/gvsoc.sh
cd ..
Then tests can be compiled and run as for the RTL platform. "

Best Regards,

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  How to do post-synthesis simulation of PULPino after generating netlist using DC
Posted by: zhouqiang - 05-09-2019, 02:19 PM - Forum: PULP General questions - Replies (2)

     We want to tape out PULPino using SMIC 0.13um technology, and now we have finished DC and got netlist of PULPino, we have generated a 32KB SRAM macro ,the ROM macro and their function mode verilog file. Next, we are going to use the netlist, the RAM and ROM to do a post-synthesis simulation of PULPino. Can someone tell me how to perform post-synthesis simulation of PULPino? Especially, how to test the functions of SRAM and ROM to determine if they are working properly?

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  [PULP] Peripheral bus memory map
Posted by: lukamac - 05-09-2019, 11:05 AM - Forum: PULP General questions - Replies (1)


I have been working on adding a HWPE to the bigpulp cluster. For start I added the HWPE MAC example into the bigpulp and synthesis passes.
Now, I would like to write an application in HERO-SDK that uses the MAC engine but I could not find the memory map for peripheral bus.

Is there a file in bigpulp which defines offsets of connected peripherals to the peripheral bus or is there any documentation about it?
To be more specific, I would like to know the base address of the HWPE and where it is defined in bigpulp.

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  clock problem when writing sdc file in order to synthesize PULPino
Posted by: zhouqiang - 05-08-2019, 12:53 PM - Forum: PULP General questions - Replies (2)

Clock problem when writing sdc file in order to synthesize PULPino

I am now trying to write a constraint file (sdc file)  to synthesize PULPino (using DC), but I don't know much about PULPino's RTL design, so it is a challenging task for me,my question is:

1. According to the .xdc file in vivado, I infer that PULPino has three asynchronous clocks clk, spi_clk_i, tck_i. What is the frequency relationship between them?

2. In DC, I use the command get_nets/ports *clk*, I also got a spi_master_clk_o, which looks like an output port. What is it used for? Do I need to constrain it?

3. In the ASIC design, I want to set the frequency of the main clock clk to 100MHz. So, how should I set the frequency for the other two clocks?

4. In addition, I also want to constrain the generated clock. Is there a generated clock in PULPino? How should I find out all the generated clocks and the corresponding source clock?

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  Pulpissimo L2 memory access via JTAG
Posted by: skor - 05-08-2019, 07:41 AM - Forum: PULP General questions - Replies (3)


I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
`define SOC_L2_START_ADDR        32'h1C00_0000
`define SOC_L2_END_ADDR          32'h1FFF_FFFF

However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from  any memory address that i have tried.
So where is the memory located actually ? 
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.

As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.

Regards, skor

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  Pulpissimo synthesis
Posted by: MikkeN - 05-07-2019, 04:19 PM - Forum: PULP General questions - Replies (5)


are you having some scripts or tools to help making correct code parsing for synthesis?
I have made my own list, but don't know which files should be included. For example there is axi_slice_dc_master_wrap.sv under axi and pulp_soc.
Is there some automation hidden for src_files.yml files under IPs and RTL?

Currently when running synthesis with dc_shell, it gives errors from some of IPs. I assume that those are not needed in Pulpino implementation.

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  RI5CY - FPGA Synthesis
Posted by: jaypi - 05-07-2019, 03:20 PM - Forum: PULP General questions - No Replies


I'm trying to synthesis the RI5CY core for my bachelor thesis.
I do work with Vivado and the Ultra 96 development board.
When importing the rtl files and checking them i do have the following error:
The fpnew_pkg with has to do with the new implementation of the FPU as i suppose is used several times, but
never declared.

Just to give one example:

CRITICAL WARNING: [HDL 9-3136] 'fpnew_pkg' is not declared

Running the synthesis fail even opting out the FPU in the risv_core.sv due to this.

Is there maybe an older build? Or where can the fpnew_pkg be found?

Do i have to declare my own fpnew_pkg?

It seems to me that the fpnew_pkg just contains some variables that the code f.e. in riscv_defines.sv:391 tries set / access.

Hopefully some of you may help me with that [Image: smile.png]

Thanks in advance!

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  [HERO] Userland application debugging
Posted by: lukamac - 05-07-2019, 09:58 AM - Forum: PULP General questions - Replies (1)


Is there a way to debug userland applications that are running on the target (board)?

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