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Some questions about the ...
Forum: PULP General questions
Last Post: Olivier
Yesterday, 03:38 PM
» Replies: 0
» Views: 20
Pulpissimo prepare standa...
Forum: PULP General questions
Last Post: bluewww
06-03-2020, 03:08 PM
» Replies: 3
» Views: 437
Target options for PULP R...
Forum: PULP General questions
Last Post: bluewww
06-03-2020, 03:06 PM
» Replies: 1
» Views: 53
The status of Ariane ARA ...
Forum: PULP General questions
Last Post: kgf
05-26-2020, 08:51 AM
» Replies: 1
» Views: 139
how to manipulating of GP...
Forum: PULP General questions
Last Post: bbr49
05-08-2020, 08:13 AM
» Replies: 4
» Views: 2,403
How to find the signal wh...
Forum: PULP General questions
Last Post: ninipa
04-26-2020, 02:48 PM
» Replies: 2
» Views: 488
using axi from rtl and C ...
Forum: PULP General questions
Last Post: sake
04-23-2020, 06:37 PM
» Replies: 3
» Views: 1,049
Modifying bootloader to l...
Forum: PULP General questions
Last Post: LPLA
04-22-2020, 03:39 PM
» Replies: 0
» Views: 360
Accelerator HWPE Example ...
Forum: PULP General questions
Last Post: acastillo
04-20-2020, 02:21 PM
» Replies: 0
» Views: 388
Editor to use with pulpis...
Forum: PULP General questions
Last Post: sake
04-18-2020, 04:21 PM
» Replies: 5
» Views: 811

 
  Some questions about the HERO platform
Posted by: Olivier - Yesterday, 03:38 PM - Forum: PULP General questions - No Replies

Hello,

I'm new to using the PULP environment and currently I am trying to familiarize myself with the HERO platform implemented on my ZC706 board and I have a few questions:

• I saw that with OpenMP the workload to execute is sent to the cluster with 8 RISC-V cores.
However, can I choose precisely which cores will be used to run a workload ?
For example, I would like the workload W1 to be executed by cores PE0, PE1 and PE2 and the workload W2 to be executed by cores PE M to PE N-1.

• I suppose it is possible with the ZC706 FPGA board to have 2 clusters of 4 RISC-V cores.
Similar to the previous question, can I choose which cluster will run a workload ?

• I saw in the file "fe/rtl/includes/pulp_soc_defines.sv" on Github that it is possible to define an FPU. But I can't find the apu_package.sv file mentioned in the comment on line 45 to add an FPU.
Is it possible to add an FPU in big-pulp?
Is the FPU shared between the cores or is it one FPU per core ?

• Last question, Is it possible to add a HWCE to a cluster ?


Thanks in advance

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Question Target options for PULP RISC-V GNU Compiler Toolchain
Posted by: mehrdad - 06-03-2020, 02:35 PM - Forum: PULP General questions - Replies (1)

Hi,

I have build the PULP RISC-V GNU Compiler Toolchain [1] with multilib. It contains the following targets:

Code:
$ riscv32-unknown-elf-gcc --print-multi-lib
rv32imfcxpulpv2/ilp32;@march=rv32imfcxpulpv2@mabi=ilp32
rv32imfcxpulpv2/ilp32f;@march=rv32imfcxpulpv2@mabi=ilp32f
rv32imcxpulpslim/ilp32;@march=rv32imcxpulpslim@mabi=ilp32
rv32ic/ilp32/mreg16;@march=rv32ic@mabi=ilp32@mreg=16
rv32imcxgap8/ilp32;@march=rv32imcxgap8@mabi=ilp32
rv32imcxgap9/ilp32;@march=rv32imcxgap9@mabi=ilp32

Using PULPissimo's pulp-configs for the processor IPs [2] I could get some info about the targets but still, I have few questions about these targets:
  • march=rv32ic, mreg=16:
    This is used for Micro-riscy. What is the difference compared to march=rv32ec of RISC-V GNU Compiler Toolchain [3]?
  • march=rv32imfcxpulpv2:
    Is this rv32imfc plus the extra instructions introduced in RI5CY? (e.g. hw loops)
  • march=rv32imcxpulpslim:
    What is this? I saw it has been used for zero-riscy [4]. What is the difference to rv32imc or rv32emc?
Thanks and kind regards,
Mehrdad

[1] https://github.com/pulp-platform/pulp-ri...-toolchain
[2] https://github.com/pulp-platform/pulp-co.../ips/riscv
[3] https://github.com/riscv/riscv-gnu-toolchain
[4] https://github.com/pulp-platform/pulp-tr...8/Makefile

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  The status of Ariane ARA vector processor?
Posted by: roychen - 05-26-2020, 08:42 AM - Forum: PULP General questions - Replies (1)

How are ARA open source going?



Best Regard,
Roy

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  Pulpissimo prepare standalone flash image
Posted by: bbr49 - 05-07-2020, 02:31 PM - Forum: PULP General questions - Replies (3)

I'm trying to simulate standalone booting from flash using the bootsel=0 and the bootrom.
What are the steps to prepare an image starting from the compiled elf file?
Do I just need to load it as is in the flash model for simulation, or are there some additional steps required?

Is there some documentation regarding this topic?

Thanks !

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  How to find the signal which represents 16bit instructions in the design?
Posted by: ninipa - 04-26-2020, 01:37 PM - Forum: PULP General questions - Replies (2)

Hi,

I'm trying certain software debug tool on pulpissimo. To build alignment between source code and disassembly, I need to trace both "pc" and the corresponding "instruction" in the design during runtime.
I've found the "pc" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.pc_id_i[31:0]"
And probably the "inst" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.instr[31:0]"

For example, on "hello" case, a piece of disassembly is:
   

The waveform is like:
   

you can see when the instruction is 32bit, disassembly is matched with waveform (eg. pc=0x1c008130, inst=0x82f72a23)
But when the instruction is 16bit, looks like I can find a signal in waveform to show the 16bit instruction correctly... for example, pc=0x1c008134, disassembly shows the instruction val=0xc69c; but the 32bit "inst" signal shows different value in the waveform...
Instead, I find the 16bit inst at output of L2 ram... But I can't use the output of L2 ram in my tool since it's too hard to align with pc...

any ideas?

Thank you!


Hi,

I just read RISCV manual, looks like these 16bit instructions are RV32C instructions? Then it's decoded into 32bit instruction in the design and the signal "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.instr[31:0]" is the decoded one, right?
So my question becomes --- can you point me the signal which cycle aligned with certain "pc" signal and the value is original?

Thank you!

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  Modifying bootloader to load data from flash memory to different L2 addresses
Posted by: LPLA - 04-22-2020, 03:39 PM - Forum: PULP General questions - No Replies

Hello,

I'm currently trying to understand how the booting process works (PULPissimo) and if I can modify it in a way that data gets moved from the flash memory to different locations in the L2 memory during this process.

This is similar to how booting from flash already works but the difference is that my flash does not only contain the image of the code that i want to run but also additional data that needs to be loaded in an accelerators memory once.

After loading the image into the flash i boot from flash using STANDALONE.
Of course everything works fine for a simple code like the hello example from the pulp_rt_examples.
I simulate using QuestaSim and get the expected "Hello !" output at the end.

The tricky part is that the additional data for my accelerator needs to be loaded to specific address(es) in the L2 memory.
For example i want to load X bytes from 0x00010000@flash to 0x1c030000@L2 and Y bytes from 0x00110000@flash to 0x1c040000@L2 and so on.
That's the basic idea behind what i want to do.

I'd like to know if it is possible to have my data from flash loaded to L2 during the boot phase in the way i described.
There are a couple of things that are still unclear to me:

1
The GitHub page mentions that:

Quote:Boot from ROM is not available yet. The ROM will always return the code jal x0,0 to trap the core until the debug module takes over control and loads the programm into L2 memory.
This is mentioned in the FPGA section but I'm not sure how up-to-date this is and if this is also true for non FPGA scenarios.

2
I have not been able to find the linker script or startup code in either the PULPissimo or the pulp-builder directory, only a few assembly startup code files. The setup I'm working with is slightly different than the GitHub version so it can be confusing trying to compare them by simply looking for certain files which might be needed in one version but not the other one. For example: The version I'm currently working with has a bootloader.c file which is the startup code but i couldn't find such a file in the GitHub version.


I hope my question is a bit clearer now as basically all I'm trying do to is loading data from flash to L2 during boot phase (like it already does in the STANDALONE boot mode) but in my case I also have additional data which needs to be moved to certain addresses in L2.



Edit: Rephrased nearly the entire question.

Thank you,
LPLA

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  Accelerator HWPE Example Loops on ZedBoard
Posted by: acastillo - 04-20-2020, 02:21 PM - Forum: PULP General questions - No Replies

Hello,

Right now I am trying to run the accelerator example on the zedboard, but right now I have a issue regarding of running the application. For some reason after this line of code __rt_periph_wait_event(ARCHI_SOC_EVENT_FCHWPE0, 1), the application loops. What can be a good approach to fix it?



[Image: 79639808-3dc6cf80-818e-11ea-84ad-879a3098e98e.png]

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  Debug Boot code
Posted by: ninipa - 04-16-2020, 04:07 AM - Forum: PULP General questions - Replies (4)

Hi,

I migrated pulpissimo simulation env to a synthesizable env. I removed tb part so there is no JTAG action (but I confirmed the clocks are all fine in the system). bootsel has been set to 1'b1.
Even without the JTAG action, I expect at least boot-code can run correctly.
But, via compare PC (tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.pc_id_i[31:0]) value in golden simulation and my simulation. I found that after several instructions, my simulation jumped to another branch, like:
golden sim: .... 0x1a0002dc -> 0x1a0002de -> 0x1a0002e0 -> 0x1a0002e4 -> 0x1a0002e6 -> 0x1a000316 -> .....
my sim:      .... 0x1a0002dc -> 0x1a0002de -> 0x1a0002e0 -> 0x1a0002e4 -> 0x1a0002e6 -> 0x1a0002e8 -> .....
before that, the PC value and sequence is exactly the same

Now my problem of debugging it is: ./sim/boot/boot_code.cde is already made as hex file. I can find the src boot-code at https://github.com/pulp-platform/boot-code, but when I try to make executable, it is invoking "pulp-runtime/install/rules/pulp_properties.mk" but it's not there... (I want to make exe and then objdump it to debug with disassembly)

Can you please point me how to generate the corresponding disassembly to boot_code.cde? Or can you simply help me figure out why my simulation fails with the PC sequence I provided? 

Thank you!

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  Add custom instruction
Posted by: nayan - 04-08-2020, 04:31 PM - Forum: PULP General questions - Replies (1)

I downloaded pulp riscv gnu toolchain and pulp sdk. I there a way to add a custom instruction to the riscv cross compiler?

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  Cannot run hello,c on GDB when connected to Ariane via JTAG
Posted by: anouarnechi - 04-08-2020, 03:01 PM - Forum: PULP General questions - Replies (3)

Hi
I want to run simple hello.c example So I compiled as following:
riscv64-unknown-elf-gcc hello.c -L linker.lds -o hello.elf
where linker.lds is :

Code:
ENTRY(main)

SECTIONS
{
  // I changed this to the DRAM start addr (0x80000000)
  ROM_BASE = 0x80000000; /* ... but actually position independent */

  . = ROM_BASE;

  .text.init : { *(.text.init) }

  .text : ALIGN(0x100) {
  _TEXT_START_ = .;
      *(.text)
  _TEXT_END_ = .;
  }

  .data : ALIGN(0x100) {
  _DATA_START_ = .;
      *(.data)
  _DATA_END_ = .;
  }

  PROVIDE(_data = ADDR(.data));
  PROVIDE(_data_lma = LOADADDR(.data));
  PROVIDE(_edata = .);

  .bss : ALIGN(0x100) {
  _BSS_START_ = .;
      *(.bss)
  _BSS_END_ = .;
  }

  .rodata : ALIGN(0x100) {
  _RODATA_START_ = .;
      *(.rodata)
      *(.dtb*)
      *(.rodata*)
  _RODATA_END_ = .;
  }
}

and the compilation was successful. Then, I followed the instructions in GITHUB  connected with success to JTAG. the problem that I cannot run the the hello.elf I can only see the disassemble which looks correct. check what I tried:

Code:
~/Desktop/ariane_test/hello$ riscv64-unknown-elf-gdb hello.elf
GNU gdb (GDB) 8.3.50.20191012-git
Copyright (C) 2019 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv64-unknown-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
   <http://www.gnu.org/software/gdb/documentation/>.

For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from hello.elf...
(gdb)  target remote localhost:3333
Remote debugging using localhost:3333
0x0000000000010044 in ?? ()
(gdb) load
Loading section .text, size 0xc0a2 lma 0x100b0
Loading section .rodata, size 0xdb8 lma 0x1c160
Loading section .eh_frame, size 0x4 lma 0x1d000
Loading section .init_array, size 0x10 lma 0x1d008
Loading section .fini_array, size 0x8 lma 0x1d018
Loading section .data, size 0x1100 lma 0x1d020
Loading section .sdata, size 0x58 lma 0x1e120
Start address 0x00000000000100c2, load size 57294
Transfer rate: 53 KB/sec, 5729 bytes/write.
(gdb) target exec
A program is being debugged already.  Kill it? (y or n) y
No executable file now.
(gdb) target exec hello.elf
(gdb) load
You can't do that when your target is `exec'
(gdb) run
Don't know how to run.  Try "help target".
Could you please help me, I want to see 'Hello Ariane' printed on the console
Thank you

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