Hey everyone 

I am trying to set up an I2C on my NEXYS 4 board without using the rt api from the sdk.
Now I think I have understood the way how the uDMA works an I am also able to transmitt something over the I2C (clock is there and a signal on the SDA is there too), but this are 
not the data I wanted to transfer.

My main problem now is, I am not able to write the address of my TX buffer to the TX_SADDR register. In the manual I can see that the TX_SADDR should be a read/write register but writing to it seams not be possible.
Does someone know what the problem could be or is there maybe an example how to setup peripherals connected to the uDMA without the help of the rt api?

Would really appreciate your help.

Thank you very much and have a nice day.

Hello, We are trying to design a ultra low-power microcontroller for IoT applications in a 0.18um CMOS technology and I am trying to decide to choose the PULPino or PULPismo platform.
PULPino seems like the more matured platform but PULPismo seems to be the replacement for PULPino.
Our core strength is analog so we want a platform which has a well-supported toolchain, etc.
So any advice on this topic will be greatly appreciated.

Hi,

I ran the cv32e40p (RI5CY) core with FPU (floating point) enabled and tried to check the result for all the floating-point operations. I have faced the following issues incase of division and fused operations.

• Rounding mode output is incorrect for division, rounding mode for the division is not the same as addition, subtraction, and multiplication
  For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
• Exception status flags output is incorrect for division, exception status flags output for the division is not the same as addition, subtraction, and multiplication, and doesn't follow IEEE754
  For example, the overflow flag is not generated even if the division result generated is infinity (for MAX/MIN case).
• Rounding mode output is incorrect for fused operations, rounding mode for fused operations is not the same as addition, subtraction, and multiplication
  For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
• Getting output as X in fused operations if any of the operands is 0
  For example, If any of the 3 operands are 0 in FMA, the result generated by the core is X.

we are facing a problem in full duplex communication in riscv pulpissimo  ,i.e. we can not start  reception after transmission using the spansion s25fs256s spi module . Could you please give some ideas regarding that. Or could you please give us a document regarding that

Hi,
Are there any documents or codes available to write Interrupt Service Routine for Pulpissimo in C language?

Scanf, gets, getchar etc. are showing undefined reference error while compiling a program using pulp-sdk. Is there anyway to get input from console?

Hi,
I am trying to simulate CV32E40P core. In example_tb file in core folder there is a make file. It is showing error


vlib-"10.7b" work
/bin/sh: 1: vlib-10.7b: not found
make: *** [Makefile:87: .lib-rtl] Error 127

I read in the documentation that there is a separate repository for verification. I have run the makefile in core-v-verif/cv32/sim/core. i was able to run hello world program. But i dont why in CV32E40P core it was not running.

I wanted to explore floating point unit in CV32E40P core. Can you please say how to simulate with system verilog files

I am not able to understand how to give input to the core. Please help me

Thanks in advance

Hi, I'm new to this and got some errors when generating the bitstream file.

The code I ran:

I successfully got Pulpissimo with RISCY working on the Digilent ARTY-A7-100T board, running the "Hello" example using the pulp-SDK. Yeeey!

I configured RISCY to not use a floating point unit, by setting:

• Does this mean floating point instructions are potentially still being generated?
  

• If so, how do I make the toolchain aware that RISCY was configured without FP unit?
  

Hi, All:
I followed the instruction to setup a simple run environment, but always failed at the build stage, with following messages:

** Error: ../ips/pulp_soc/rtl/pulp_soc/soc_interconnect.sv(22): Cannot find `include file "axi/assign.svh" in directories:

    ../ips/pulp_soc/../../rtl/includes, ../ips/pulp_soc/rtl/include, ../ips/pulp_soc/../axi/axi/include, /eda/Mentor/Questa10.7/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src, /eda/Mentor/Questa10.7/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src

I checked all cloned files, found AXI, dm, ... etc, NOT downloaded. 

Could you someone help me on this issue?