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» Forum threads: 259
» Forum posts: 796

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Latest Threads
Compiling and running CNN...
Forum: PULP General questions
Last Post: NEO
04-11-2024, 12:29 PM
» Replies: 2
» Views: 143
How do I get the files ne...
Forum: PULP General questions
Last Post: AlessioBurrello
04-05-2024, 10:22 AM
» Replies: 1
» Views: 296
Pulpissimo bitstream gene...
Forum: PULP General questions
Last Post: zealshah29
03-28-2024, 06:41 AM
» Replies: 13
» Views: 40,094
Help to run Hello Example
Forum: PULP General questions
Last Post: zealshah29
03-28-2024, 06:31 AM
» Replies: 5
» Views: 10,618
Compiling and running app...
Forum: PULP General questions
Last Post: zealshah29
03-28-2024, 06:13 AM
» Replies: 5
» Views: 18,572
Understanding the TCDM in...
Forum: PULP General questions
Last Post: zealshah29
02-13-2024, 10:34 AM
» Replies: 7
» Views: 14,885
Error while updating IPs
Forum: PULP General questions
Last Post: zealshah29
02-08-2024, 06:03 AM
» Replies: 4
» Views: 9,738
Snitch cluster: make bin/...
Forum: PULP General questions
Last Post: ashuthosh
02-07-2024, 07:38 AM
» Replies: 1
» Views: 411
Synthesizable Version of ...
Forum: PULP General questions
Last Post: cykoenig
01-16-2024, 10:52 AM
» Replies: 2
» Views: 739
RISC V proyect research
Forum: PULP General questions
Last Post: kgf
12-29-2023, 01:09 PM
» Replies: 1
» Views: 735

 
  Compiling and running CNNs on FPGA(pulp)
Posted by: NEO - 04-04-2024, 12:33 AM - Forum: PULP General questions - Replies (2)

Hi, Is it possible to compile and run CNNs on FPGA (pulp)? If so, could you direct me to a guide or tutorial on how to achieve this? This information is crucial for my work.

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  How do I get the files needed for a custom model to be deployed on PULP?
Posted by: NEO - 02-29-2024, 12:36 AM - Forum: PULP General questions - Replies (1)

Hi, I am trying to deploy a custom model on the PULP platform. So far, I have successfully quantized the custom model and generated the ".onnx" file through the NEMO. However, while generating the network through the "network_generate.py" file under the DORY, I get an error: "out_layer0.txt not found". How can I get the required ".txt" files such as "input.txt",  "out_layer0.txt", "out_layer1.txt" and so on? Also, I would like to know if the ".json" file containing information about the model parameters can be generated automatically. Or do I have to fill it in manually? I would be very grateful for your reply!

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  Snitch cluster: make bin/snitch_cluster.vlt error
Posted by: ashuthosh - 02-06-2024, 08:44 AM - Forum: PULP General questions - Replies (1)

I have built the docker and cloned the snitch_cluster repo in /repo.
And then in the target/snitch_cluster, I use the command make bin/snitch_cluster.vlt

For which I get:
work-vlt/Vtestharness.h:11:10: fatal error: verilated_heavy.h: No such file or directory


What am I doing wrong here?


Commands I have used:
   

  1. To build docker:
    Code:
    sudo docker build -t ghcr.io/pulp-platform/snitch_cluster:main -f util/container/Dockerfile .
    2.  In the snitch_cluster root: docker run -it -v $REPO_TOP:/repo -w /repo ghcr.io/pulp-platform/snitch_cluster:main
    3.  In /repo of docker: git clone https://github.com/pulp-platform/snitch_cluster.git --recurse-submodules
    4.  In /repo/snitch_cluster/target/snitch_cluster: make bin/snitch_cluster.vlt


Thanks in advance.

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  Synthesizable Version of the HERO Project Accelerator
Posted by: ajgaspar - 01-05-2024, 08:43 PM - Forum: PULP General questions - Replies (2)

When trying to run the setup for RTL simulation of the HERO Project's accelerator through synthesis, two modules are not synthesizable, namely axi_sim_mem and apb_stdout. Are there preexisting versions of these two modules that will pass synthesis, or would I just have to try and make them synthesizable while trying to maintain the default functionality as much as possible? TIA

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Photo Failed to connect to pulpissimo via jtag
Posted by: cern143 - 12-23-2023, 04:10 AM - Forum: PULP General questions - No Replies

Hi,
I tried to connect to pulpissimo via jtag using openocd, but always get this error:
   
I tried on 2 different fpgas: zedboard and zcu104 and get the same error. This is my openocd config file:
   
I have been struggle with this error for weeks and really need help :<

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  RISC V proyect research
Posted by: Alejandro.p_00 - 12-01-2023, 01:39 PM - Forum: PULP General questions - Replies (1)

Hello everyone,

Im currently doing a research for a future proyect about RISC V based core IPs,  chips, devboards fully designed and manufactured in Europe that are being commercialized right now. Preferable if the devboard counts with multiple communication protocols, no FPGAs, less 25W consumption, no SoC.
If in development I  would also appreciate the information. I know SiFive is selling european designed and manufactured RISC V dev boards, but, the RISC V chips themselfs are manufactured in China.

Thank you in advance for the assistance.

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  PULPino Boot ROM Address problem
Posted by: Jay Huang - 11-30-2023, 03:28 AM - Forum: PULP General questions - Replies (1)

Hi, I am Jay Huang, a Verification Engineer at Taiwan Electronic System Design Automation (TESDA). Currently, we are utilizing your open-source SOC, PULPino, to develop our verification tools.

During the course of our SOC implementation, we have encountered some challenges related to the PULPino Boot ROM, prompting us to seek clarification on certain aspects. According to the datasheet Memory Map, the Boot ROM's address range is specified as 0x0008_0000 to 0x0008_0200.

In an attempt to integrate this information into our testbench, I observed that when attempting to read from this address range, no data was retrieved. After further investigation, it was determined that the Boot ROM is, in fact, located immediately following the Instruction Memory, rather than at the specified address.

I would like to ask if it is correct to set the start address of the Boot ROM at 0x0000_8000 if the Instruction Memory is configured as 32KB?
If this configuration is indeed correct, I am curious as to why the Boot ROM's address in the datasheet is documented as 0x0008_0000 to 0x0008_0200.

Your insights and guidance on this matter would be immensely valuable to us in resolving the issues we are currently facing. Thank you for your time and attention to this inquiry.

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  Changing Pulpissimo core to cv32e40s
Posted by: ivanhira - 11-21-2023, 07:39 PM - Forum: PULP General questions - Replies (1)

Hi, 

I was trying to implement a solution to add AES and maybe other crypto extensions in Pulpissimo. I tried to change the core to a variant of the RI5CY, CV32E40S that support some of that extensions. 
When I run a test that worked on the original core, the JTAG halts the core in the simulation. 

I was wondering if there is something to do with the SDK (by the way, i'm using this platform for a while so i'm still using releases 7.0 and pulp-sdk) or the toolchain to make it work, or is it just a problem in the connection of the core. There are quite a few more ports so, just to start trying, I left some of the ports that seemed optional from the documentation. 

Thanks in advance.

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  Pulpino without PS
Posted by: istillaga - 11-20-2023, 08:52 AM - Forum: PULP General questions - Replies (1)

Hello,

I am trying to generate pulpino's bitstream without using the processing system loading the programs via SPI SLAVE. I modified the pulpemu folder deleting all the processing system's part and I managed to generate the bitstream but I am getting this warnings:

WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0__0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__1 input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mac input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mul input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/p_0_out input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mac output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mul output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/p_0_out output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (ZPS7-1) PS7 block required - The PS7 cell must be used in this Zynq design in order to enable correct default configuration.

Then with Vivado I transfer the bitstream to the zedboard and send the code to load the program via SPI SLAVE but I don't get any answer from MISO and it doesn't load the program.

Any help?

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  about windows vivado
Posted by: ZruiQian - 11-03-2023, 06:51 AM - Forum: PULP General questions - No Replies

One question I have is whether I can deploy pulp with vivado for windows

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