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Interrupt handling proble...
Forum: PULP General questions
Last Post: nikolas
Yesterday, 08:54 AM
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I2C cannot write to TX_SA...
Forum: PULP General questions
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03-03-2021, 11:07 AM
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PULPino or PULPismo ? for...
Forum: PULP General questions
Last Post: sit-vlsi
03-01-2021, 11:46 AM
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Queries in FPU for cv32e4...
Forum: PULP General questions
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02-25-2021, 08:05 PM
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Getting input from consol...
Forum: PULP General questions
Last Post: nayan
02-25-2021, 12:35 PM
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Interrupt Service Routine...
Forum: PULP General questions
Last Post: RiscV
02-24-2021, 09:16 AM
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Question about bitstream ...
Forum: PULP General questions
Last Post: zorrolee777
02-23-2021, 08:22 PM
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using axi from rtl and C ...
Forum: PULP General questions
Last Post: meggiman
02-23-2021, 02:20 PM
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fullduplex communication ...
Forum: PULP General questions
Last Post: chikku
02-23-2021, 07:27 AM
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pulp-rt-example Makefile ...
Forum: PULP General questions
Last Post: nikolas
02-18-2021, 03:39 PM
» Replies: 1
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  I2C cannot write to TX_SADDR
Posted by: nikolas - 03-03-2021, 11:07 AM - Forum: PULP General questions - No Replies

Hey everyone 

I am trying to set up an I2C on my NEXYS 4 board without using the rt api from the sdk.
Now I think I have understood the way how the uDMA works an I am also able to transmitt something over the I2C (clock is there and a signal on the SDA is there too), but this are 
not the data I wanted to transfer.

My main problem now is, I am not able to write the address of my TX buffer to the TX_SADDR register. In the manual I can see that the TX_SADDR should be a read/write register but writing to it seams not be possible.
Does someone know what the problem could be or is there maybe an example how to setup peripherals connected to the uDMA without the help of the rt api?

Would really appreciate your help.

Thank you very much and have a nice day.

Code:
//in a headerfile called pulpissimo.h
#define I2C0_RX_SADDR    (*((volatile uint32_t *)0x1A102180))
#define I2C0_RX_SIZE    (*((volatile uint32_t *)0x1A102184))
#define I2C0_RX_CFG    (*((volatile uint32_t *)0x1A102188))
#define I2C0_TX_SADDR    (*((volatile uint32_t *)0x1A102190))
#define I2C0_TX_SIZE    (*((volatile uint32_t *)0x1A102194))
#define I2C0_TX_CFG    (*((volatile uint32_t *)0x1A102198))

//in hal_i2c.c
__attribute__((section(".l2_data"))) uint8_t tx_buff[BUFFERSIZE];
__attribute__((section(".l2_data"))) uint8_t rx_buff[BUFFERSIZE];
__attribute__((section(".l2_data"))) uint8_t cmd_buff[BUFFERSIZE];

//in an initialisation function in hal_i2c.c
I2C0_RX_SADDR  |= (uint32_t)&rx_buff[0]; //after this there is 0x00000000 in the register
I2C0_RX_SIZE   |= BUFFERSIZE;            //after this there is 0x00000000 in the register
  
I2C0_TX_SADDR  |= (uint32_t)&tx_buff[0]; //after this there is 0x00000000 in the register
I2C0_TX_SIZE   |= BUFFERSIZE;            //after this there is 0x00000000 in the register

I2C0_CMD_SADDR |= (uint32_t)&cmd_buff[0]; //after this there is 0x00000000 in the register
I2C0_CMD_SIZE  |= BUFFERSIZE;             //after this there is 0x00000000 in the register

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  PULPino or PULPismo ? for a low-power microcontroller
Posted by: sit-vlsi - 02-28-2021, 03:01 PM - Forum: PULP General questions - Replies (3)

Hello, We are trying to design a ultra low-power microcontroller for IoT applications in a 0.18um CMOS technology and I am trying to decide to choose the PULPino or PULPismo platform.
PULPino seems like the more matured platform but PULPismo seems to be the replacement for PULPino.
Our core strength is analog so we want a platform which has a well-supported toolchain, etc.
So any advice on this topic will be greatly appreciated.

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  Queries in FPU for cv32e40p
Posted by: mlmram - 02-25-2021, 06:10 PM - Forum: PULP General questions - Replies (1)

Hi,

I ran the cv32e40p (RI5CY) core with FPU (floating point) enabled and tried to check the result for all the floating-point operations. I have faced the following issues incase of division and fused operations.

  • Rounding mode output is incorrect for division, rounding mode for the division is not the same as addition, subtraction, and multiplication
    For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
  • Exception status flags output is incorrect for division, exception status flags output for the division is not the same as addition, subtraction, and multiplication, and doesn't follow IEEE754
    For example, the overflow flag is not generated even if the division result generated is infinity (for MAX/MIN case).
  • Rounding mode output is incorrect for fused operations, rounding mode for fused operations is not the same as addition, subtraction, and multiplication
    For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
  • Getting output as X in fused operations if any of the operands is 0
    For example, If any of the 3 operands are 0 in FMA, the result generated by the core is X.
Please let me know if these are the bugs in the core or the FPU, or if there's anything wrong with my understanding of floating-point operations.

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  fullduplex communication in spi through spansion s25fs256s
Posted by: chikku - 02-23-2021, 07:27 AM - Forum: PULP General questions - No Replies

we are facing a problem in full duplex communication in riscv pulpissimo  ,i.e. we can not start  reception after transmission using the spansion s25fs256s spi module . Could you please give some ideas regarding that. Or could you please give us a document regarding that

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  Interrupt Service Routine for Pulpissimo
Posted by: RiscV - 02-22-2021, 09:09 AM - Forum: PULP General questions - Replies (2)

Hi,
Are there any documents or codes available to write Interrupt Service Routine for Pulpissimo in C language?

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  Getting input from console
Posted by: nayan - 02-19-2021, 05:33 AM - Forum: PULP General questions - Replies (4)

Scanf, gets, getchar etc. are showing undefined reference error while compiling a program using pulp-sdk. Is there anyway to get input from console?

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  how to simulate CV32E40P core
Posted by: gsaitejareddy - 02-08-2021, 08:11 AM - Forum: PULP General questions - Replies (2)

Hi,
I am trying to simulate CV32E40P core. In example_tb file in core folder there is a make file. It is showing error


vlib-"10.7b" work
/bin/sh: 1: vlib-10.7b: not found
make: *** [Makefile:87: .lib-rtl] Error 127

I read in the documentation that there is a separate repository for verification. I have run the makefile in core-v-verif/cv32/sim/core. i was able to run hello world program. But i dont why in CV32E40P core it was not running.

I wanted to explore floating point unit in CV32E40P core. Can you please say how to simulate with system verilog files

I am not able to understand how to give input to the core. Please help me

Thanks in advance

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  Question about bitstream generation
Posted by: zorrolee777 - 02-04-2021, 06:24 PM - Forum: PULP General questions - Replies (4)

Hi, I'm new to this and got some errors when generating the bitstream file.

The code I ran:

Code:
$ cd $COREVMCU/fpga
$ make clean_nexys rev=nexysA7-100T
$ make nexys rev=nexysA7-100T
After running the above codes, I got the following errors.
Code:
ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:48]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_slow_clk_gen' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:24]
ERROR: [Synth 8-6156] failed synthesizing module 'safe_domain' [/home/core-v-mcu/rtl/pulpissimo/safe_domain.sv:12]
ERROR: [Synth 8-6156] failed synthesizing module 'pulpissimo' [/home/core-v-mcu/rtl/pulpissimo/pulpissimo.sv:13]
ERROR: [Synth 8-6156] failed synthesizing module 'xilinx_pulpissimo' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v:22]


When I commented out the module, some other errors would come out, saying those modules are not found. I guess there're four of them, which are xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. I'm not sure if those modules are supposed to be generated by myself, or where should I get and put them? Any comments would be appreciated. Thanks in advance!

Sincerely,
Zorro

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  Compiling for RISCY without FP?
Posted by: LarsKeuninckx - 01-27-2021, 10:56 AM - Forum: PULP General questions - Replies (2)

I successfully got Pulpissimo with RISCY working on the Digilent ARTY-A7-100T board, running the "Hello" example using the pulp-SDK. Yeeey! Smile

I configured RISCY to not use a floating point unit, by setting:

Code:
localparam USE_FPU  = 0;

in xilinx_pulpissimo.v.

However, the gcc commands of the "Hello" example, following "make clean all", contain:

Code:
... -march=rv32imfcxpulpv2 -mfdiv ...


So the questions are: 
  • Does this mean floating point instructions are potentially still being generated?
  • If so, how do I make the toolchain aware that RISCY was configured without FP unit? Huh

Additional info: the toolchain was setup using the instructions at https://github.com/pulp-platform/pulp-ri...ation-pulp.


Thanks!

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  Failed at building the RTL simulation platform
Posted by: Jackie Zhang - 01-25-2021, 11:58 AM - Forum: PULP General questions - Replies (4)

Hi, All:
I followed the instruction to setup a simple run environment, but always failed at the build stage, with following messages:

** Error: ../ips/pulp_soc/rtl/pulp_soc/soc_interconnect.sv(22): Cannot find `include file "axi/assign.svh" in directories:

    ../ips/pulp_soc/../../rtl/includes, ../ips/pulp_soc/rtl/include, ../ips/pulp_soc/../axi/axi/include, /eda/Mentor/Questa10.7/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src, /eda/Mentor/Questa10.7/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src

I checked all cloned files, found AXI, dm, ... etc, NOT downloaded. 

Could you someone help me on this issue?

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