hi,
 
I tried running interfaced GPIO with the test cases given in PULPino environment. after running testcases I am getting has test case  failed. why test failed occurs.

** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_RXFF
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_TXFF
# Using MEMLOAD method: PRELOAD
# Using      ri5cy core
# [SPI] Enabling QPI mode
# [adv_dbg_if] AXI4 WRITE         32 burst @1a107008 for           4 bytes.
# Preloading memory
# Preloading instruction memory from slm_files/l2_stim.slm
# Preloading data memory from slm_files/tcdm_bank0.slm
# [TRACER] Output filename is: trace_core_00_0.log    
#[SPI] Received 00000003
#[SPI] Test  Failed
# **Note :$Stop   


THANKS IN ADVANCE   

Good afternoon,

After several issues I have been able to install the complete SDK and platforms. 

I'm able to compile applications and run them on the rt platform. I'm also able to complete the Vivado implementation of Pulpissimo for the Zedboard. However, I'm still not able to run applications on the Zedboard.

The sequence of steps I carry out are:

1 - Using Vivado Hardware manager I program the device on the Zedboard with the pulpissimo-zedboard.bit configuration file. Everything is fine, the device is configured and led LED0 is on (from the .xdc file and xilinx_pulpissimo.v I identify that this is CSN for SPI channel 1, so it is OK).

2 - source configs/pulpissimo.sh

3 - source configs/fpgas/pulpissimo/genesys2.sh (from the information provided in GitHub there shoulb be also a zedboard.sh script, but this is the only one that can be found)

4 - source sourceme.sh

5 - make clean all

6 - The USB cable that was used to configure the Zynq device is removed from the Zedboard.

7 - The Digilent JTAG-HS2 cable is attached to PMOD A.

8 - openocd -f openocd-zedboard-hs2.cfg

9 - riscv32-unknown-elf-gdb FILENAME

10 - (gdb) target remote localhost:3333

11 - (gdb) load

If within gdb I issue two list commands here is what I get:

1 /*
2 * This example shows how drive a GPIO as an output.
3 */
4
5 #include <stdio.h>
6 #include <rt/rt_api.h>
7 #include <stdint.h>
8
9 #define GPIO 20
10
(gdb) list
11 int __rt_fpga_fc_frequency = 20000000; // e.g. 20000000 for 20MHz;
12 int __rt_fpga_periph_frequency = 10000000; // e.g. 10000000 for 10MHz;
13
14 int main()
15 {
16  unsigned long i;
17
18  // First configure the SPI device
19  rt_spim_conf_t conf;
20  // Get default configuration

Now I want to place a breakpoint at line 19. Therefore what I get is:

(gdb) b 19
No line 19 in the current file.
Make breakpoint pending on future shared library load? (y or [n]) 

Therefore, it seems that something is wrong. If I issue the command 'continue' on gdb I get the message Continuing, and nothing happens.

I have tried the same flow, but issuing a 'source platform-fpga.sh' after step 4, but the result is the same.

Can you identify if something is missing or wrong in the steps I'm following? Any help will be appreciated.

In order to check if the program is being executed properly by Pulpissimo on the Zedboard I'm trying to turn OFF LED0 by changing the value of the CSN signal of SPI channel 1 that is mapped onto this LED, but without success until now.

Best regards,

Manuel

Do anyone try running UART testcase(already available testUART.c) in PULPino?

I tried it but the simulation never ends, why so?. can anyone help me on this 

I am getting the following in my transcript window

** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_RXFF
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_TXFF
# Using MEMLOAD method: PRELOAD
# Using      ri5cy core
# [SPI] Enabling QPI mode
# [adv_dbg_if] AXI4 WRITE         32 burst @1a107008 for           4 bytes.
# Preloading memory
# Preloading instruction memory from slm_files/l2_stim.slm
# Preloading data memory from slm_files/tcdm_bank0.slm
# [TRACER] Output filename is: trace_core_00_0.log

hi

How to see waveforms in questasim while running the given testcases. I tried to add the signals to waveform window, but I am not able to do it. Is there any command available?.

Hello,

I'm trying to install PULP-SDK following the instructions provided in GitHub, but I get an error I can't understand and for which I haven't found any solution.

I'm starting from a clean Ubuntu 16.04 install, and the sequence of steps I follow (first I install the riscv gnu toolchain and then the PULP SDK) is:

1 - sudo -s

2 - apt install git python3-pip python-pip gawk texinfo libgmp-dev libmpfr-dev libmpc-dev swig3.0 libjpeg-dev lsb-core doxygen python-sphinx sox graphicsmagick-libmagick-dev-compat libsdl2-dev libswitch-perl libftdi1-dev cmake scons libsndfile1-dev

3 - pip3 install artifactory twisted prettytable sqlalchemy pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

4 - sudo pip2 install configparser

5 - cd /opt

6 - mkdir riscv

7 - cd riscv

8 - git clone https://github.com/pulp-platform/pulp-ri...-toolchain

9 - cd pulp-riscv-gnu-toolchain

10 - git submodule update --init --recursive

11 - apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev

12 - export PATH=$PATH:/opt/riscv/bin

13 - ./configure --prefix=/opt/riscv --with-arch=rv32imc --with-cmodel=medlow --enable-multilib

14 - make

15 - export PULP_RISCV_GCC_TOOLCHAIN=/opt/riscv

16 - export VSIM_PATH=/opt/riscv/pulpissimo/sim

17 - cd ..

18 - git clone https://github.com/pulp-platform/pulp-sdk.git -b master

19 - cd pulp-sdk

20 - source configs/pulpissimo.sh

21 - make all

After this last command I get the following error:

Configuring Pulp project at /opt/riscv/pulp-sdk
Traceback (most recent call last):
  File "./pulp-tools/bin/plpbuild", line 3, in <module>
    import plptools as plp
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plptools.py", line 27, in <module>
    from plpobjects import *
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plpobjects.py", line 32, in <module>
    from openpyxl import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/__init__.py", line 6, in <module>
    from openpyxl.workbook import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/workbook/__init__.py", line 4, in <module>
    from .workbook import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/workbook/workbook.py", line 7, in <module>
    from openpyxl.worksheet.worksheet import Worksheet
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/worksheet/worksheet.py", line 392
    return f"{get_column_letter(min_col)}{min_row}:{get_column_letter(max_col)}{max_row}"
                                                                                        ^
SyntaxError: invalid syntax
Makefile:6: recipe for target 'all' failed
make: *** [all] Error 1

Following the instructions provided in GitHub I check the versions of both python and pip. What I get is:

root@VBox:/opt/riscv/pulp-sdk# pip --version
pip 19.3.1 from /usr/local/lib/python2.7/dist-packages/pip (python 2.7)
root@VBox:/opt/riscv/pulp-sdk# python3 --version
Python 3.5.2

Then I execute the commands suggested in GitHub:

python3 -m pip install --upgrade pip
python3 -m pip install artifactory twisted prettytable sqlalchemy pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

However, when I run again 'make all' I get the same error. Since after looking for a solution I haven't found any clue how to fix it, could you provide me any hint to overcome this problem? Thank you very much in advance for your help.

Best regards,

Manuel

Hi,

I have problems using the JTAG debugging connection with GDB for the Ariane Softcore. The Genesys 2 Board is connected to my PC via JTAG. I have OpenOCD with RISC-V support  installed on my machine and it seems to connect just fine:

Hi,

In PULPino environment there are some HEX Files getting generated while i tried to run testcase. So my query is where the conversion from C to HEX file is taking place (code & path). 

thanks in advance.

(11-25-2019, 07:10 AM)mahalakshmir.ma Wrote: Hi,

In PULPino environment there are some HEX Files getting generated while i tried to run testcase. So my query is where the conversion from C to HEX file is taking place (code & path). 

thanks in advance.

hi,
 while simulating GPIO in questasim I am getting following error.
please tell me why this occurs and how to resolve it.


thankyou

Hi all, 

First of all, thanks a lot for your help and support.

I was wondering if there is a synthesis - clean version of PULPissimo that's already released to the public. If not, is there any document / way to understand how the clock the distribution is going ? 

What I understand, correct me if I am wrong, that in the case of: 

1- FPGA, u r using a reference clock of 200 MHz to generate two internal clocks by divisions: A- Soc_clk = 20Mhz , B- periph_clk = 10Mhz.

2- In case of the RTL simulation, you r feeding from the TB a reference clock of ~ 32KHz and somehow, using DCO, FLL generating two clocks soc_clk = periph_clk = 17.5 MHz. 

If I am correct, are this on-chip clock generation modules synthesizable? Or they should be mapped to IPs in the PDK ? 

--------- 

Assuming that I want to drive the whole chip using the external clock, is it save to just remove all the " fll, DCO.. etc" modules and pass the signal through the modules to all the system components ? I mean the PAD_xtal_clk, pass it for the fc_subsystem, l2_memory .. etc and the system can work on that clock ? I already did simulation and it worked, but I am making sue that I didn't miss anything as I didn't test the system exhaustively. 

Thanks in advance.

Hi,

I tried to include a new peripheral (PWM) into the PULPino environment, where can I get the library files for that peripheral or it will be auto generated.