Hi,

I want to connect a camera to Pulpissimo's Camera Interface (CPI) on Genesys2 board.  However, most CPI pads are connected to LEDs/buttons/switches on Genesys2 board.  Can I modify the constraints file to remap and connect the CPI signals to the FMC connector so that I can use Digilent FMC Pcam Adapter to connect camera modules?  Any considerations I need to take ?

Thanks,

tparng

Hi, 

I have been trying to program Nexys A7 with the latest Pulpissimo RTL and I am encountering these issues, any clue? 

1. REPORT DETAILS
   

Hello,

I am very interested in using the HERO platform for research, especially on its hrv variant and the VCU128 implementation that is mentioned in the Readme file of the Github repository. It says that it is "under development", but the repository has not had any updates in the last months. Is it still being developed? Is there any other place to look at that I may have missed?

Any kind of guidance or help to advance in that direction would also be greatly appreciated, because it does not seem to be an easy task without some prior knowledge of the platform. I have tried to start from an older port on the Genesys 2 but there seem to be some missing parts.

Thank you in advance. BR,

Pedro Lobo.

I started working with Pulpissimo and I saw that the SDK is not supported any more.
Currently, I was working with the simple runtime and the runtime examples but there are only 3 of them.
Is there any way I could get more examples, dma, timers, gpio ...?  
Is there a way to build the old pulpissimo sdk (branch v1) vene if it is not supported anymore?

Hello,

I would like to deploy the pulp-platform in an Artix fpga but I don't know what files to include in the design and simulation, as well.
Are there any tree file which explains how the files are connected on RTL and Simulation level so that know which is the top level ?

Hello,

getting acquainted with PULP platform these last few weeks - so, first of all, a big thank you and a bigger congratulations to all the creators and contributors.

I haven't had prior experience with tools such gvsoc, so I am bit troubled by trying to wrap my head around where are its limits, actually - hence this post. Please, any clarifications in this discussion would be of great help.

First of all, I've seen the videos from pulp training:

1. Understanding and working with PULP
   
2. GVSoC / Dory Tutorial
   
3. A Deep Dive into HW/SW Development with PULP
   

Hello,

I get this error while I am trying to build the RTL.

How to perform regression test when the compiler is replaced with LLVM, The compiler used by the existing regression test is GCC. I want to compile it with clang to run the regression test. Or, there are other test sets to test whether the clang compiler can correctly generate the instruction of pulp.

Hello! I'm interested in creating custom extensions to the RISC-V ISA. The goal of these extensions would be to define instructions that perform specific operations (e.g., butterfly operations, twiddle factor generation, modular arithmetic) that I can use to implement various cryptographic primitives (e.g., NTT). I would then like to measure the speedup of these cryptographic primitives with my extensions enabled vs. with my extensions disabled.

What would be the best platform to achieve this goal?

I see one possibility, which is to take the CV32E40P core and extend it with custom functional units using SystemVerilog. I'd then have to find a way to get the compiler to take advantage of the new instructions that I've defined.

While I would be comfortable using SystemVerilog, I'm more interested in exploring the design space of possible instructions rather than attempting to debug a particular hardware design. For this reason, I'm curious if an architectural simulator / instruction set simulator would be more appropriate for my needs. Does PULP offer an architectural simulator / instruction set simulator? I found GVSoC, but I'm not sure if it's what I'm looking for.

Any advice would be greatly appreciated. Thank you!

Hi,
looking at website, I see several cores have been taped out.
I'm trying to find more info in how tape out has been carried out.
Is the tape out flow fully based on the RTL of the cores (the one available on GitHub repos) or human circuit customization has been
performed ?
For example, looking at https://github.com/openhwgroup/cv32e40p core I see the register file is described at high level as a simple array.
When it comes to circuit implementation has the synthesis  had free room to decide how to translate the RF in real digital circuit or some human
customization has been carried out?