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PULPissimo FLL bypass
Forum: PULP General questions
Last Post: Happybug
02-06-2023, 02:00 PM
» Replies: 7
» Views: 8,830
Latest Pulpissimo RTL doe...
Forum: PULP General questions
Last Post: kgf
01-31-2023, 03:53 PM
» Replies: 3
» Views: 232
Can I remap Pulpissimo pa...
Forum: PULP General questions
Last Post: tparng
01-09-2023, 02:02 PM
» Replies: 2
» Views: 244
Status / roadmap of HERO ...
Forum: PULP General questions
Last Post: kgf
12-22-2022, 11:15 AM
» Replies: 1
» Views: 330
Pulpissimo Tests or Pulpi...
Forum: PULP General questions
Last Post: Happybug
12-14-2022, 10:01 AM
» Replies: 0
» Views: 231
Role of gapy, list of per...
Forum: PULP General questions
Last Post: nanoluka
12-06-2022, 10:05 AM
» Replies: 6
» Views: 1,149
Architecture file hierarc...
Forum: PULP General questions
Last Post: bgeorge
11-25-2022, 10:22 AM
» Replies: 4
» Views: 1,023
Error during building RTL
Forum: PULP General questions
Last Post: bgeorge
11-18-2022, 11:37 AM
» Replies: 3
» Views: 929
How to perform regression...
Forum: PULP General questions
Last Post: lcx1092968411
11-15-2022, 07:43 AM
» Replies: 0
» Views: 334
Custom extensions to the ...
Forum: PULP General questions
Last Post: kgf
10-09-2022, 03:56 PM
» Replies: 1
» Views: 753

 
  Can I remap Pulpissimo pads to connect a camera on Genesys2 fpga board?
Posted by: tparng - 01-07-2023, 02:11 PM - Forum: PULP General questions - Replies (2)

Hi,

I want to connect a camera to Pulpissimo's Camera Interface (CPI) on Genesys2 board.  However, most CPI pads are connected to LEDs/buttons/switches on Genesys2 board.  Can I modify the constraints file to remap and connect the CPI signals to the FMC connector so that I can use Digilent FMC Pcam Adapter to connect camera modules?  Any considerations I need to take ?

Thanks,

tparng

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  Latest Pulpissimo RTL doesn't fit the nexysA7-100T FPGA
Posted by: AhmedZaky - 01-05-2023, 01:40 PM - Forum: PULP General questions - Replies (3)

Hi, 

I have been trying to program Nexys A7 with the latest Pulpissimo RTL and I am encountering these issues, any clue? 


  1. REPORT DETAILS

UTLZ-1#1 Error
Resource utilization - PBlock:ROOT
RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 288 of such cell types but only 270 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#2 Error
Resource utilization - PBlock:ROOT
RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#3 Error
Resource utilization - PBlock:ROOT
RAMB36E1 over-utilized in Top Level Design (This design requires more RAMB36E1 cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:



Regards,

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  Status / roadmap of HERO with RV host and VCU128 port
Posted by: pedro.lobo - 12-21-2022, 02:40 PM - Forum: PULP General questions - Replies (1)

Hello,

I am very interested in using the HERO platform for research, especially on its hrv variant and the VCU128 implementation that is mentioned in the Readme file of the Github repository. It says that it is "under development", but the repository has not had any updates in the last months. Is it still being developed? Is there any other place to look at that I may have missed?

Any kind of guidance or help to advance in that direction would also be greatly appreciated, because it does not seem to be an easy task without some prior knowledge of the platform. I have tried to start from an older port on the Genesys 2 but there seem to be some missing parts.

Thank you in advance. BR,

Pedro Lobo.

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  Pulpissimo Tests or Pulpissimo SDK
Posted by: Happybug - 12-14-2022, 10:01 AM - Forum: PULP General questions - No Replies

I started working with Pulpissimo and I saw that the SDK is not supported any more.
Currently, I was working with the simple runtime and the runtime examples but there are only 3 of them.
Is there any way I could get more examples, dma, timers, gpio ...?  
Is there a way to build the old pulpissimo sdk (branch v1) vene if it is not supported anymore?

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  Architecture file hierarchy
Posted by: bgeorge - 11-22-2022, 11:17 AM - Forum: PULP General questions - Replies (4)

Hello,

I would like to deploy the pulp-platform in an Artix fpga but I don't know what files to include in the design and simulation, as well.
Are there any tree file which explains how the files are connected on RTL and Simulation level so that know which is the top level ?

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  Role of gapy, list of peripherals and capabilities of gvsoc
Posted by: nanoluka - 11-21-2022, 01:59 PM - Forum: PULP General questions - Replies (6)

Hello,

getting acquainted with PULP platform these last few weeks - so, first of all, a big thank you and a bigger congratulations to all the creators and contributors.

I haven't had prior experience with tools such gvsoc, so I am bit troubled by trying to wrap my head around where are its limits, actually - hence this post. Please, any clarifications in this discussion would be of great help.

First of all, I've seen the videos from pulp training:

  1. Understanding and working with PULP
  2. GVSoC / Dory Tutorial
  3. A Deep Dive into HW/SW Development with PULP
and I've downloaded the VM and played a bit, followed along the steps demonstrated in the GVSoC/Dory video. All works great - I got the instructions dissasembled, saw the waveforms.

Now, I am getting confused with gapy... what is that, actually? It is mentioned, listed as a tool, but its purpose eludes me... I tried looking for other resources online, but I couldn't form a picture. At first, I though that's a python library that serves as a sort of a glue between the RTL pieces... at some point in the video, it is spoken about python generators... is that it?

In the next video (A deep dive...), I see that IP dependencies are treated using a tool called IPApprox, however - that was back then, while today this is the task of bender, if I am correct. However, where is this list of IPs? In the video, there's a subdirectory IPs of the pulpissimo repo, but I don't see it there: https://github.com/pulp-platform/pulpissimo

Finally, this gvsoc - if I am getting the idea correctly, it is a cycle-accurate simulator, meaning that it can simulate execution of RISCV instructions on a PULP hardware and yield dissasembled instructions, signal waveforms and metrics, such CPI. However, is it a stone carved thing, in the sense that it can simulate only a predefined configuration of pulpissimo SoC? In other words, can it be changed without QuestaSim so that simulates execution of a PULP program on an SoC configuration with SPI and without UART, say?

I think I am pretty sure that, if I want to add novel, arbitrary RTL, then I must have QuestaSim. But if I want to play with pulpissimo SoC configuration (adding or removing some of the existing peripherals), can this be done without QuestaSim, just using gvsoc? It seemed to me that the part where (in the lecture GVSoC tutorial) it is shown how to run with and without cluster is the response to this, but - I didn't get how to exclude uart and then include spi, for example?

Thanks!

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  Error during building RTL
Posted by: bgeorge - 11-18-2022, 10:49 AM - Forum: PULP General questions - Replies (3)

Hello,

I get this error while I am trying to build the RTL.

Code:
~/workspace/pulp$ make scripts
curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \
    | bash -s -- 0.25.2
bender-init: Warning: No release for platform 'x86_64-linux-gnu-ubuntu22.04' version '0.25.2' found, using latest.
bender-init: Failed to download 'https://github.com/pulp-platform/bender/releases/download/v0.26.1/bender-0.26.1-x86_64-linux-gnu-ubuntu22.04.tar.gz'!
make: *** [Makefile:247: bender] Error 1

Can you please let me know what I am doing wrong ?


Solution:

I must change the bash version in the Makefile.
Code:
bender: ifeq (,$(wildcard ./bender))    
curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \        
| bash -s -- 0.26.1    
touch bender endif

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  How to perform regression test when the compiler is replaced with LLVM
Posted by: lcx1092968411 - 11-15-2022, 07:43 AM - Forum: PULP General questions - No Replies

How to perform regression test when the compiler is replaced with LLVM, The compiler used by the existing regression test is GCC. I want to compile it with clang to run the regression test. Or, there are other test sets to test whether the clang compiler can correctly generate the instruction of pulp.

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  Custom extensions to the RISC-V ISA
Posted by: froggyhopper50 - 10-09-2022, 03:27 PM - Forum: PULP General questions - Replies (1)

Hello! I'm interested in creating custom extensions to the RISC-V ISA. The goal of these extensions would be to define instructions that perform specific operations (e.g., butterfly operations, twiddle factor generation, modular arithmetic) that I can use to implement various cryptographic primitives (e.g., NTT). I would then like to measure the speedup of these cryptographic primitives with my extensions enabled vs. with my extensions disabled.

What would be the best platform to achieve this goal?

I see one possibility, which is to take the CV32E40P core and extend it with custom functional units using SystemVerilog. I'd then have to find a way to get the compiler to take advantage of the new instructions that I've defined.

While I would be comfortable using SystemVerilog, I'm more interested in exploring the design space of possible instructions rather than attempting to debug a particular hardware design. For this reason, I'm curious if an architectural simulator / instruction set simulator would be more appropriate for my needs. Does PULP offer an architectural simulator / instruction set simulator? I found GVSoC, but I'm not sure if it's what I'm looking for.

Any advice would be greatly appreciated. Thank you!

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  PULP CORE TAPE OUT
Posted by: giumaug - 09-29-2022, 08:09 AM - Forum: PULP General questions - Replies (1)

Hi,
looking at website, I see several cores have been taped out.
I'm trying to find more info in how tape out has been carried out.
Is the tape out flow fully based on the RTL of the cores (the one available on GitHub repos) or human circuit customization has been
performed ?
For example, looking at https://github.com/openhwgroup/cv32e40p core I see the register file is described at high level as a simple array.
When it comes to circuit implementation has the synthesis  had free room to decide how to translate the RF in real digital circuit or some human
customization has been carried out?

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