Hi,
I am trying to synthesize the pulpissimo, I don't find any documentation or specific script for post-synthesis simulation but I have done the below steps
1) replaced the generic_memory, generic_rom with technology-related cells
2) synthesized soc_domain as top and have obtained synthesis netlist and its sdf file
3) I have replaced the soc_domain.sv with the synthesis netlist in sim/vcompile/rtl/pulpissimo.mk <-- all other files are same, not sure which files to keep and which one to remove
3) I have added the CORE and CLK libs with -L option in sim/tcl_files/run.tcl
The modules gf2_fll , pulp_clock_gating , pulp_clock_mux2 , cluster_clock_gating , cluster_clock_inverter, pulp_clock_inverter are not synthesized, is any one these modules need to be synthesized for post-synthesis simulation?
what libraries should i need to keep in ./sim/tcl_files/config/vsim_ips.tcl ?
I just took my first step in scientific research focused on Xilinx ZC706 Evaluation Boards. Recently I find your PULP website https://pulp-platform.org/hero/doc/downloads/images/zc706/ . I appreciate your sharing these files here, but when I downloaded them to SD card and started the development board, I found that you did not publish the system login account and password of this example image files.
So could you please send me the login and password of the image files in the website?Or send a new boot image for zc706? I would be sincerely appreciated if you could help . Thank you very much!
Hi, I have some problems with the synthesis of Pulpissimo to ZedBoard target.
ERROR -> "an enum variable may only be assigned to same enum typed variable or one of its values [pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]"
I previously ran ./update-ips and and the ./generate-scripts. I'm running a webpack licensed 2020.2 version under Linux (Ubuntu 18.04). Do you know where is the problem?
I attach the complete log file "vivado.txt"
Code:
Starting synth_design
Using part: xc7z020clg484-1
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_private_ram/ip/xilinx_private_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
Top: xilinx_pulpissimo
INFO: [Device 21-403] Loading part xc7z020clg484-1
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_merge with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_merge.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:32]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_mux2 [/home/diego/Documents/tfm/pulpissimo/ips/tech_cells_generic/src/deprecated/pulp_clk_cells_xilinx.sv:53]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_gating [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/pulp_clock_gating_xilinx.sv:11]
ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 7 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
INFO: [Common 17-206] Exiting Vivado at Tue Mar 23 19:31:02 2021...
Makefile:11: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard'
Makefile:52: recipe for target 'zedboard' failed
make: *** [zedboard] Error 2
I notice that Pulp seems to ship with a 2015 version of COIN's CLP/CBC tools. Anyone have a good link showing how to update the COIN tools that ship with Pulp? I'm mostly on Win10.
I would like to know if anyone tried to synthesize the Pulpissimo SoC on a PYNQ-Z1 (Zynq-7000) board. The chip is almost the same that is in the zedboard (XC7Z020-1CLG400C) so I though that it would be relatively easy. If so, I would like to know what parameters or files I have to change or rewrite to achieve the compatibility, or how to proceed. As you can see, I am a beginner on this project, Do you know where to start?
Hi,
I want to use the IBEX core with pulpissimo. I was able to run Hello World example with default ri5cy core. I changed the following files by making CORE_TYPE as 1 to get the ibex core configured.
once the change was done i cleaned the pulpissimo libs with make clean and did make build
i also cleaned the pulp-sdk with 'make clean' and did
export PULP_CURRENT_CONFIG=pulpissimo_ibex@config_file=chips/pulpissimo/pulpissimo_ibex.json
source configs/pulpissimo_ibex.sh
make build env # to rebuild the pulp-sdk with ibex configs
source sourceme.sh # to set path of newly built sdk with ibex core
when I run the hello world example I get an error from the ID stage of the IBEX Core pipeline like
Hi,
I am currently working with L2 Memories. I notice that even though the size of the stimuli file I have is larger than the total size of L2 private memory (0x1c010000). The compiler does not throw l2 overflowed by ... bytes error. i have not changed the /my-path/pulp-sdk/pkg/sdk/dev/install/rules/pulpissimo/link.ld file.
This the command the make file of hello example uses to compile my code
I notice the pulp_tap exceeding the maximum address of the L2 memory
[pulp_tap_if] WRITE32 burst @1c00f800 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c00fc00 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c010000 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c010400 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c010800 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c010c00 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c011000 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c011400 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c011800 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c011c00 for 1024 bytes.
Any idea why the pulp_gnu_toolchain did not throw any error. does the pulp_gnu_toolchain should be rebuilt because i am playing by extending the Private memory sizes although the above error was produced with no change in the pulpissimo or pulp-sdk code
pulpissimo/pulp-rt-examples/gpio/input/build/pulpissimo/test/fc/test.o: In function `rt_gpio_set_dir':
pulpissimo/pulp-rt-examples/gpio/input/test.c:13: undefined reference to `__builtin_pulp_OffsetedRead'
pulpissimo/pulp-rt-examples/gpio/input/test.c:13: undefined reference to `__builtin_pulp_OffsetedWrite'
pulpissimo/pulp-rt-examples/gpio/input/test.c:13: undefined reference to `__builtin_pulp_OffsetedRead'
pulpissimo/pulp-rt-examples/gpio/input/test.c:13: undefined reference to `__builtin_pulp_OffsetedWrite'
pulpissimo/pulp-rt-examples/gpio/input/build/pulpissimo/test/fc/test.o: In function `main':
pulpissimo/pulp-rt-examples/gpio/input/test.c:13: undefined reference to `__builtin_pulp_OffsetedRead' collect2: error: ld returned 1 exit status
Any suggestion if it is possible use API without pulp specific instructions? or any work around ?
Thank you..
