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axi_xbar integration issu...
Forum: PULP General questions
Last Post: malik775
07-12-2024, 05:46 PM
» Replies: 0
» Views: 25
issue with pulp build
Forum: PULP General questions
Last Post: kgf
07-03-2024, 08:46 PM
» Replies: 1
» Views: 149
i have some issue with si...
Forum: PULP General questions
Last Post: sungyong
06-17-2024, 04:03 AM
» Replies: 0
» Views: 173
Is there any RTL generato...
Forum: PULP General questions
Last Post: sungyong
06-17-2024, 03:55 AM
» Replies: 2
» Views: 348
install issue with pulpis...
Forum: PULP General questions
Last Post: sungyong
06-04-2024, 06:23 AM
» Replies: 3
» Views: 560
ELF Files for Polybench T...
Forum: PULP General questions
Last Post: kgf
05-24-2024, 11:38 AM
» Replies: 1
» Views: 318
OpenOCD Error with Nexys ...
Forum: PULP General questions
Last Post: NEO
04-25-2024, 06:26 AM
» Replies: 1
» Views: 1,578
Booting Pulpissimo from S...
Forum: PULP General questions
Last Post: kgf
04-25-2024, 06:19 AM
» Replies: 1
» Views: 369
how to manipulating of GP...
Forum: PULP General questions
Last Post: zealshah29
04-19-2024, 12:15 PM
» Replies: 6
» Views: 18,874
priviliged interrupts
Forum: PULP General questions
Last Post: tswaehn
04-16-2024, 01:43 PM
» Replies: 0
» Views: 331

 
  axi_xbar integration issue
Posted by: malik775 - 07-12-2024, 05:46 PM - Forum: PULP General questions - No Replies

I am encountering an issue while using an AXI crossbar in my project, which has 2 slave ports and 1 master port. In the project, I have two DMAs accessing a single memory for read operations. I am using the PULP AXI_XBAR, and although it simulates, I am experiencing an error where the crossbar directs all request response data to one DMA. It correctly decodes read addresses from both DMAs but sends the response data to only one DMA. Can anyone guide me on this issue? Here is the crossbar configuration:
// AXI Configuration
localparam axi_pkg::xbar_cfg_t XbarCfg = '{
    NoSlvPorts: 2,
    NoMstPorts: 1,
    MaxMstTrans: 20,
    MaxSlvTrans: 10,
    FallThrough: 1'b0,
    LatencyMode: axi_pkg::CUT_ALL_AX,
    PipelineStages: 2,
    AxiIdWidthSlvPorts: 2,
    AxiIdUsedSlvPorts: 2,
    UniqueIds: 1'b0,
    AxiAddrWidth: AddrWidth,
    AxiDataWidth: DataWidth,
    NoAddrRules: 1
};

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  issue with pulp build
Posted by: sungyong - 06-27-2024, 11:24 AM - Forum: PULP General questions - Replies (1)

Hello, pulp community

i have some issue on build pulp, (i just succeed pulpissimo, then i'm trying to build pulp)

https://github.com/pulp-platform/pulp

i trying to build pulp with above link. But when i command "make build"

it makes error 

Makefile:30: warning: overriding recipe for target '/root/pulp/sim/tcl_files/config/vsim_ips.tcl'
Makefile:30: warning: ignoring old recipe for target '/root/pulp/sim/tcl_files/config/vsim_ips.tcl'
make -C sim all
make[1]: Entering directory '/root/pulp/sim'
make -C ../rtl/tb/remote_bitbang clean
make[2]: Entering directory '/root/pulp/rtl/tb/remote_bitbang'
rm -rf librbs.so remote_bitbang.o sim_jtag.o ./.d
make[2]: Leaving directory '/root/pulp/rtl/tb/remote_bitbang'
rm -r work
rm modelsim.ini
chmod: cannot access 'modelsim.ini': No such file or directory
make[1]: *** [Makefile:57: lib] Error 1
make[1]: Leaving directory '/root/pulp/sim'
make: *** [Makefile:120: build] Error 2



in some communities, they said commented "rm modelsim.ini"
so i make that code commented

then it has error 

# source compile.tcl
# Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
# ** Error (suppressible): (vlog-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.
# Errors: 1, Warnings: 0
# 1
#  quit
vopt +acc=npr -o vopt_tb tb_pulp -floatparameters+tb_pulp -work work
Questa Intel Starter FPGA Edition-64 vopt 2023.3 Compiler 2023.07 Jul 17 2023
** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
Start time: 20:22:08 on Jun 27,2024
vopt "+acc=npr" -o vopt_tb tb_pulp -floatparameters+tb_pulp -work work

Top level modules:
        tb_pulp

Analyzing design...
** Error: (vopt-13130) Failed to find design unit 'tb_pulp'.
        Searched libraries:
            work
Optimization failed
End time: 20:22:08 on Jun 27,2024, Elapsed time: 0:00:00
Errors: 1, Warnings: 1
make[1]: *** [Makefile:41: opt] Error 2
make[1]: Leaving directory '/root/pulp/sim'
make: *** [Makefile:120: build] Error 2

how can i fix it? the error vlog-12110, i think its problem of questasim.

How about second one? why they find design unit tb_pulp?



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  i have some issue with simulation examples.
Posted by: sungyong - 06-17-2024, 04:03 AM - Forum: PULP General questions - No Replies

Hello everyone

i just have started pulpissimo simulation examples "hello"

but when i simulate it, there's some error at last with illeagal instructions.

how can i fix it? is there any more ips that i didn't know?(because it doesn't acknowledge instruction)

# [PULP] 1110801ns - WRITE32 burst @1c000000 for        1024 bytes.
# [PULP] 1940901ns - WRITE32 burst @1c000400 for        1024 bytes.
# [PULP] 2771001ns - WRITE32 burst @1c000800 for        1024 bytes.
# [PULP] 3332301ns - WRITE32 burst @1c000c00 for        688 bytes.
# [PULP] 4162401ns - WRITE32 burst @1c008000 for        1024 bytes.
# [PULP] 4992501ns - WRITE32 burst @1c008400 for        1024 bytes.
# [PULP] 5822601ns - WRITE32 burst @1c008800 for        1024 bytes.
# [PULP] 6652701ns - WRITE32 burst @1c008c00 for        1024 bytes.
# [PULP] 7482801ns - WRITE32 burst @1c009000 for        1024 bytes.
# [PULP] 8312901ns - WRITE32 burst @1c009400 for        1024 bytes.
# [PULP] 9143001ns - WRITE32 burst @1c009800 for        1024 bytes.
# [PULP] 9973101ns - WRITE32 burst @1c009c00 for        1024 bytes.
# [PULP] 10169601ns - WRITE32 burst @1c00a000 for        232 bytes.
# [PULP] 10372501ns - WRITE32 burst @1c010000 for        240 bytes.
# [TB  ] 10374101ns - Resuming the CORE
# [TB  ] 10947601ns - retrying debug reg access
# [TB  ] 10976901ns - retrying debug reg access
# [TB  ] 11006201ns - retrying debug reg access
# [TB  ] 11035501ns - retrying debug reg access
# [TB  ] 11064801ns - retrying debug reg access
# [TB  ] 11094101ns - retrying debug reg access
# [TB  ] 11123401ns - retrying debug reg access
# [TB  ] 11152701ns - retrying debug reg access
# [TB  ] 11196701ns - Waiting for end of computation
# [STDOUT-CL31_PE0] [RT(31,0)] WARNING: Reached illegal instruction (PC: 0x1c008e2c, opcode: 0x20230001
# [TB  ] 12114201ns - Received status core: 0x7fffffff
# ** Note: $stop    : /pulpissimo/rtl/tb/tb_pulp.sv(776)
#    Time: 12114201 ns  Iteration: 0  Instance: /tb_pulp
# Break in Module tb_pulp at /pulpissimo/rtl/tb/tb_pulp.sv line 776
# Stopped at /pulpissimo/rtl/tb/tb_pulp.sv line 776
# End time: 11:56:12 on Jun 17,2024, Elapsed time: 0:11:17
# Errors: 0, Warnings: 10
Launching simulator with command:


=====added=======

i check the dump file with make dis
then i found that nop operation is illegal, how can i fix it?

1c008e20: 15a60613 addi a2,a2,346 # 1c00815a <udma_event_handler>
1c008e24: 00a250fb lp.setupi x1,10,1c008e2c <__rt_periph_init+0x1c>
1c008e28: 00c6a22b p.sw a2,4(a3!)
1c008e2c: 0001 nop
1c008e2e: 28072023 sw zero,640(a4)
1c008e32: 28072223 sw zero,644(a4)

thx!



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  Is there any RTL generator for pulp platform?
Posted by: sungyong - 06-03-2024, 09:59 AM - Forum: PULP General questions - Replies (2)

helllo,

i just tried pulp platform and i've done simulation with pulp-sdk and pulp
By the way, i want to develop pulp cores. Is there any RTL generator? i've seen rocket chip with chisel language. 
Is there any same things like chisel in pulp-platform?

Then, if i want to modify some modules at pulp-platform, there's only way to do is modify system verilog code? 

Thanks for reading. Smile

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  ELF Files for Polybench Tests
Posted by: ajgaspar - 05-23-2024, 11:29 PM - Forum: PULP General questions - Replies (1)

I currently have the design set up to run the included polybench tests, but I would like to have the ELF files as well for each respective test if possible. Are they included anywhere in the repo? TIA

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  install issue with pulpissimo
Posted by: sungyong - 05-13-2024, 06:02 AM - Forum: PULP General questions - Replies (3)

I got this error when command : make build

vopt +acc -o vopt_tb tb_pulp -work work
Error: cannot find "/root/intelFPGA/20.1/modelsim_ase/bin/../linux/vopt"
make[1]: *** [Makefile:69: opt] Error 1
make[1]: Leaving directory '/pulpissimo/sim'
make: *** [Makefile:121: build] Error 2

is there anyone have same issue? i think the modelsim has vopt folder on ~/modelsim_ase/bin/vopt



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  Booting Pulpissimo from SPI - post silicon
Posted by: ivanhira - 04-22-2024, 06:01 PM - Forum: PULP General questions - Replies (1)

Hi, 

I have a Pulpissimo chip we sent to a foundry to manufacture. It was synthesized based on pulpissimo releases v7.0.0. We have managed to run a couple of tests on 20MHz.
The problem is when trying to boot from SPI by forcing '00' on bootsel, the spi pads does not respond. We have tried keeping the jtag connector on or disconnecting it from the board. 

Also, on Questasim, when trying to boot from a mode different than the specified from the RTL, e.g., STANDALONE and SPI_FLASH on tb_pulp.sv and forcing '00' on bootsel in the simulation, the transcript posts Branch decision X, when trying to load the 2nd page. The flash content is erased because I did not call the simulation with the arguments to load the program on the flash, but still it should get the error after loading the program and trying to run it, right?

I appreciate if there are any suggestions on how we can make the boot work.

Thanks in advance, Ivan.

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  priviliged interrupts
Posted by: tswaehn - 04-16-2024, 01:43 PM - Forum: PULP General questions - No Replies

I am using the machine and user mode on the pulp (CV32E40P). As far as I understand I need to set UTVEC and MTVEC to the corresponding locations of interrupt vector table. I also registered a handler for ex timer (machine mode handler + user mode handler individiually) and enabled the timer. Then I can enable the interrupts in MSTATUS or USTATUS. 

My observation is: 
* when beeing in user mode => interrupts are pushed to UTVEC and handled in user mode
* when beeing in machine mode => interrupts are pushed to MTVEC and handled in machine mode

However I was expecting some kind of configuration where all interrupts are preferably handled by machine mode (always) => where and how can I configure this? (I expected some implementation of medeleg and mideleg, but this doesnt seem to exist?)

any hints are welcome. thank you in advance.


***update***

if I leave the user interrupt in USTATUS disabled, then in both modes the handler of machine mode will be triggered. however as the user can enable the user interrupt in USTATUS, I would still expect the machine mode handler to be triggered with higher priority - thus should be triggered first => but that is not happening.

***hints***

Quote:An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and © if register mideleg exists, bit i is not set in mideleg.

reference

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  Compiling and running CNNs on FPGA(pulp)
Posted by: NEO - 04-04-2024, 12:33 AM - Forum: PULP General questions - Replies (2)

Hi, Is it possible to compile and run CNNs on FPGA (pulp)? If so, could you direct me to a guide or tutorial on how to achieve this? This information is crucial for my work.

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  How do I get the files needed for a custom model to be deployed on PULP?
Posted by: NEO - 02-29-2024, 12:36 AM - Forum: PULP General questions - Replies (1)

Hi, I am trying to deploy a custom model on the PULP platform. So far, I have successfully quantized the custom model and generated the ".onnx" file through the NEMO. However, while generating the network through the "network_generate.py" file under the DORY, I get an error: "out_layer0.txt not found". How can I get the required ".txt" files such as "input.txt",  "out_layer0.txt", "out_layer1.txt" and so on? Also, I would like to know if the ".json" file containing information about the model parameters can be generated automatically. Or do I have to fill it in manually? I would be very grateful for your reply!

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