Hello,

We have been trying to understand how the Pulpissimo memory map is generated.
Our purpose is to add our own modules (ultra low power memory) to it and we would need to understand it.

We found that memories are defined in l2_ram_multi_bank.sv, but how to add new memory to it?

Please, can you clarify file names that need to be modified to change Pulpissimo memory map?

Br,
Akim

I can see that there is no Issues panel in pulp-sdk project on GitHub. I have some things to discuss regarding Ibex integration and I guess it would be much better place for this than this forum. In my opinion reliable SDK is one of the most important parts of the entire system, so maybe it would be nice idea to enable it for others to easily file issues and ask questions?

Hi, is there somewhere a guide how to create new SoC configuration for pulp-sdk? I'm basing on PULPissimo and just copied some files in `pulp-configs` to create custom configuration. I wonder though if there is some kind of recommended way of doing this and if there is some sort of documentation anywhere. I've seen different scripts (`pulp_chip_gen`, `pulp_soc_gen`, …), but there is no description which does what and in what scenarios one should be used.

Hi,
I would like to do some manipulation of the user and general purchase I/Os of the pianissimo platform, for example to light up a user LED via pressing down a pushbutton.
I found the functions in the sdk runtime doc for configuring the gpio as a bus such as rt_gpio_init and rt_gpio_pin_configure etc, but I did not find any document mentioning the exact address/pin or registers that are corresponding to the LEDs or pushbuttons. I am wondering where to get the detailed info of such so that I can light up a user LED?

Thanks,
Mapletree

Hi,
I have generated a Pulpissimo platform bitstream for Xilinx ZCU102 board. Now I am at the stage to compile a "hello world" example to try on the FPGA. I am having two problems here:

1. On the pulpissimo web page, after the instructions on how to create the .c file that includes the baudrate and frequency of the UART and the main() function, it gives instructions on how to compile an application by issuing " make clean all" command, but there is no corresponding Makefile, therefore, I got an error " No targets specified and no makefile found". I did all these in pulp-builder home directory. My questions are: a). is there an existing Makefile that I can borrow to compile my hello.c for RISCV?  b).  If I need to create my own Makefile, do I need to include the boot code? if so where to get the boot code (the same code in sim/boot directory)? It will be nice if there is an example Makefile that I can start with.

2. When I tried to connect to the JTAG interface on the board(JTAG pins are allocated on PMOD) by issuing the openocd command, I got an error saying "embeddedtartup.tcl:21:Error: Unknown target type riscv". The command I issued: $openocd -f openocd-zcu102-digilent-jtag-hs2.cfg. The screenshot of the error massage and the openocd config file are attached.


Please help!

Thanks,
Mapletree

Attached Files

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  openocd-zcu102-digilent-jtag-hs2.txt (Size: 667 bytes / Downloads: 1)

Hi All, 

First of all thanks for sharing the PULPissimo source codes, however I have been looking for a somehow detailed documentation for PULPissimo but I couldn't found. 

Can anyone please point me to such a documentation if any ? 

Regards,

Hello everyone,

I would like to ask you how to change memory layout of pulpissimo

My problem is that I need to use code that uses big vectors. Then, when  I run the program in the virtual platform I got:

3699418377: 147973: [/sys/board/chip/soc/fc/warning                   ] Invalid access (offset: 0x1bfffcd8, size: 0x4, is_write: 1)

Which is a problem of stack overflow. I could move big vectors to other memory sections but this implies to modify the code, which i shouldn't. Also, sometimes I got problems with the code size. So in general I would like to know how to modify the memory to be able to execute the code without modifications.

The problem can be reproduced with the following code:

Hi,

we have synthesized Pulpissimo with Vivado (2018.3) to FPGA and with Design Compiler (2018) to silicon technology.
Now Pulpissimo code has been changed so, that Design Compiler can't synthesize it anymore.
Vivado synthesize it without issues.

Module LZC gives syntax error from this statement:
assign cnt_o   = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : $clog2(WIDTH)'(0);

Also there is number of bus with conflicts which are quite painful to correct by user.

Can you make code cleaning and check that it passes Design Compiler?
I am also worried about quality of results in FPGA, because Vivado has not seen issues which exist.

Hi,
Currently I'm testing PULPino core on Altera DE10-Nano board. I want to use provided JTAG interface with Digilent HS-2 cable. There seem to be no documentation about connecting PULPino to OpenOCD anywhere so I thought to use slightly modified version of OpenOCD config from PULPissimo project as supposedly the debug interface is pretty much the same. Is it a valid assumption? So far I didn't get too far. In the attachment you can find my current OpenOCD config (I'm using your patched version based on PULPissimo README) and a log.
Is there some working solution so that it's possible to use PULPino with JTAG?

Greetings,
Marek

Attached Files

  hs2-pulpino.cfg.txt (Size: 894 bytes / Downloads: 5)
  openocd-log.txt (Size: 23.61 KB / Downloads: 6)

Hello,

What are the two registers REG_FCBOOT and REG_FCFETCH meant for? They are in Soc_control area. Basically in RTL code is said that they are not used, so because I would like to add a new register to soc_control area I was planning to use either of these . 
I would anyway like to make sure that I am not blocking anything that might be usefull later.


Regards,

skor