Hello,

We installed the SDK and the toolchain on our Linux server and have QuestaSim-64 v10.0c
 installed.
When trying to generate the PULPissimo RTL platform I am getting the following error message during the build 'phase':

** Error: ../ips/common_cells/src/stream_mux.sv(18): near "localparam": syntax error, unexpected localparam
** Error: ../ips/common_cells/src/stream_demux.sv(20): near "localparam": syntax error, unexpected localparam
** Error: ../ips/common_cells/src/popcount.sv(21): near "localparam": syntax error, unexpected localparam
make[2]: *** [modelsim_libs/common_cells_lib/common_cells_all.vmake] Error 2
make[1]: *** [build] Error 2
make: *** [build] Error 2

Do you have any clue what can be the reason for this error?

Thanks,
Ido

On the github platform for PULP, under pulp-rt-examples repository the coremark benchmark has been given. 

This benchmark runs for platforms like the single-core platform PULPissimo as well as the PULP (8 core platform). 

However, in both cases I have inferred that the platforms are running at a frequency of 100 MHz. 

For instance this is the output obtained for the Pulpissimo with zero riscy core:

[TB]          30495473188 - Triggering fetch enable
# [TRACER] Output filename is: trace_core_1f_0.log
# [dbg_if_soc] WRITE32 burst @1a104008 for           4 bytes.
# [TB]          30509373188 - Waiting for end of computation
# [STDOUT-CL31_PE0] 2K performance run parameters for coremark.
# [STDOUT-CL31_PE0] CoreMark Size    : 666
# [STDOUT-CL31_PE0] Total ticks      : 535261
# [STDOUT-CL31_PE0] Total time (usecs): 5352
# [STDOUT-CL31_PE0] Iterations/Sec   : 186
# [STDOUT-CL31_PE0] ERROR! Must execute for at least 10 secs for a valid result!
# [STDOUT-CL31_PE0] Iterations       : 1
# [STDOUT-CL31_PE0] Compiler version : na
# [STDOUT-CL31_PE0] Compiler flags   : na
# [STDOUT-CL31_PE0] Memory location  : STATIC
# [STDOUT-CL31_PE0] seedcrc          : 0xe9f5
# [STDOUT-CL31_PE0] [0]crclist       : 0xe714
# [STDOUT-CL31_PE0] [0]crcmatrix     : 0x1fd7
# [STDOUT-CL31_PE0] [0]crcstate      : 0x8e3a
# [STDOUT-CL31_PE0] [0]crcfinal      : 0xe714
# [STDOUT-CL31_PE0] Correct operation validated. See README.md for run and reporting rules.
# [STDOUT-CL31_PE0] CoreMark 1.0 : 186 / na na / STATIC
# [TB]          45796773188 - Received status core: 0x00000000
# ** Note: $stop    : /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv(679)
#    Time: 45796773188 ps  Iteration: 0  Instance: /tb_pulp
# Break at /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv line 679
# Stopped at /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv line 679
# End time: 14:51:20 on Feb 05,2019, Elapsed time: 0:05:38
# Errors: 0, Warnings: 15


From the total time taken and the total ticks fields, it can be deduced that the platform is running at a speed of 100 MHz. 

How was this frequency chosen?

Also, is there a way to change this frequency from the coremark.patch file (or any other file for that matter) that has been given with the coremark folder under pulp-rt-examples. 

Another interesting result of running the coremark example was that I obatined the same performance numbers (as listed above) for PULP and PULPissimo (with RISCY core). Does this mean that when coremark is running on PULP it is just giving the performance number of the core and the not the entire architecture? or How to interpret these values after running the coremark. Is it only evaluating the performance of a single core regardless of the platform?

Hello!


While following the instructions to install the RISC-V GNU compiler as listed here :https://github.com/pulp-platform/pulp-riscv-gnu-toolchain.

I installation for the linux cross compiler is failing.
On running this command on the terminal: 

Hi,

If I want to estimate the energy and power consumption of a specific software which is run on PULP (let's say PULPino, PULPissimo or bigPULP) with an HWPE that I added, what is the proper way of doing it?
In addition, is there a way of estimating the area?

Thanks!
Adi

Riscy and zero riscy cores based on the RISC V ISA are available as a part of different PULP systems. The specific custom extensions in the RISC V ISA are supported by the compiler. 

I was wondering If I can make changes to the RISCY core for eg adding a new h/w block like the h/w loop controller.
First of all with the given SDK is that even possible?
And is there a possibility of getting software support for such modifications. 

Thanks!

Hi,

I'm developing an HWPE which is supposed to run with BigPULP.
I want to wait for my HWPE to finish executing from my C code. In pulpissimo, I used the following code:

Greetings.

I don't have time to be eloquent, sorry.

Is there some documentation, readme or tutorial on how to use the pulp designs?
Maybe it is common knowledge in the field of digital design (like ./configure make is a common standard in software), but I am a meager noob and student and I spent lots of hours without getting anything to work.

I managed to use modelsim to compile all RI5CY sources necessary to run a simulation of tb_riscv_core, but there was no clock signal and I don't know how to load programs etc.
Maybe I was hasty but I couldn't find proper help in the repo.

Thanks.
Regards Robin.

Hi,

My goal is to run an application on PULP which passes data to my PULP accelerator (HWPE) and vice versa (I use the ARM standalone application just as a way of running my PULP application, if this is at all necessary, is it? So I don't want to share data between the ARM and PULP, but between PULP and my HWPE). 
When I simulated my accelerator on PULPissimo, my PULP application stored data in the TCDM simply by accessing a known offset (there was no virtualization), and the accelerator could access the same data with the appropriate address. I want to have the same functionality with HERO, so how do I do it? If I use addresses like in PULPissimo, what are the proper addresses? (I was advised to use 0x1b201000, but it didn't work for me) If it's more complicated than just accessing some offset, how do I do it otherwise and what Makefile I use which will work with both the HWPE API and the data sharing API?

In addition, I have another question regarding compiling a PULP application (not accelerator related). I want to use the riscv-blas library in my PULP application. This library includes Fortran code. The riscv-toolchain in the HERO environment doesn't have gfortran, so I tried to build another riscv toolchain with gfortran in order to compile the library. However, when I try to link libgfortran.a (generated with the second toolchain) to the PULP application using the HERO scripts, I get a lot of link errors about std C functions that are missing. So I was wondering, what is the proper way of compiling Fortran in a PULP application? Alternatively, if you're familiar with another solution of using BLAS on PULP, I'd appreciate if you could refer me to it.

Thanks,
Adi

Hello again!

The documentation for the ri5cy core, although getting better, is still a little "light" on details for the debugger hardware.

Is there any facility available for accessing memory whilst in debugging mode?
if not, how is it proposed that memory should be accessed when debugging?

what would be the suggested mechanism for implementing a breakpoint mechanism such the executing programme can be run up to a point then the debugger activated?
(I already have a simulation where I can single step the core at a specified simulation clock count, in reality this needs to be at a specified PC).

Thanks in advance

Hello!

I am investigating using the ri5cy core for a commercial application.
Quite some time ago I looked into the ri5cy core via the Embecosm githubu fork:
https://github.com/embecosm/ri5cy

This seems to (now) be a quite old version of the core (32 interrupt inputs, much different csr implementation).

So, I've updated my core payload with the latest ri5cy rtl build.

I now have problems with my prototype interrupt code.
In C I have:


in "main()" {
    set_csr (0x300, 0x00000009);            //enable interrupts?
    write_csr(0x305, my_isr);               // isr address?
   
    // big long delay
    for (int i=0;i<10000;i++) asm("NOP");

}

void __attribute__ ((interrupt())) my_isr (){
    *simresult = (unsigned short int) 0xF111;    // flag result
}

which gives me:
00000300 <my_isr>:
 300: ff010113           addi sp,sp,-16
 304: 00f12423           sw a5,8(sp)
 308: 00e12623           sw a4,12(sp)
 30c: 40002703           lw a4,1024(zero) # 400 <simresult>
 310: 0000f7b7           lui a5,0xf
 314: 11178793           addi a5,a5,273 # f111 <_end+0xece5>
 318: 00f72023           sw a5,0(a4)
 31c: 00c12703           lw a4,12(sp)
 320: 00812783           lw a5,8(sp)
 324: 01010113           addi sp,sp,16
 328: 10000073           eret

The compiler is inserting the correct isr handling code......
But when simulated with the latest ri5cy core I get:
#  - DGB - write 0 into CTRL
#        2465870000 ps: Illegal instruction (core 0) at PC 0x00000328:
#        2469762000 ps: Illegal instruction (core 0) at PC 0x00000328:

I read in the riscv documentation that eret should now probably be an mret.
(At present I am using the embecosm modified toolchain (gcc).)

where can I download the "official" build gcc build tools for the latest ri5cy core (including all of the ri5cy additions like the hardware loop functionality)?

Many thanks in advance