Hello，
I am a student  a complete novice in SOC design. Our tutor wants to implement a RISCV chip design on the extra area of the MPW. If I want to tape out PULPino, what should I verify first?

As far as I know, PULPino is a very mature project, and it has been taped out in different processes, so my current idea is:

1. Perform a Verilog simulation test. The assembly code of the instruction is compiled into a binary file to be read by Verilog's readmemh function, and then all instructions are tested one by one until all instructions pass the test. This part of the test should only involve the operation of the instruction set in the RISCY core.

2. Perform FPGA prototype verification on PULPino SOC. The purpose of this process is to download the SOC's Verilog code to the FPGA and then run the program on the FPGA. It may be necessary to use GDB and OpenOCD for debugging.

Is my idea correct? Does the PULPino project support the above two verifications? Can you give me some advice? And what should be noted in the tool chain, environment, SDK, etc.?

Thanks
zhouqiang

Hello,

I have been trying to Synthesize and implement Pulpissimo on Xilinx FPGA using Vivado . There are problems in the syntesized design although elaborated design seems to be Okay.  Have you synthesised Pulpissimo using VIvado and if yes then did you have to do changes to the RTL?

My synthesis basically is completed succesfully, but when I look at the synthesised schematics I can see that for example zynq_clk_i is not connected anywhere, although it should go to ref_clk_i in soc_domain.

Regards, Sirpa

Hello, 


I want to benchmark the performance of the 8 core multicore platform PULP. The current coremark example in pulp-rt-examples needs to be modified to be able to run it on PULP such that it uses the 8 cores of the cluster. Can a guideline be provided to modify the Coremark benchmark for the PULP platform. 

Regards,
Athena

Hello,

We have bought couple of Genesys2 FPGA boards. We are going to use the Pulpissimo for that.

We would like to flash the test software to it and also if possible use some debugging software via JTAG.
Do you have any suggestion to use as JTAG-cable or debugging software, that you are going to support? 
Do I need to use Genesys2 PMOD connectors to connect JTAG-cable or do you have any solid solutions for that?

If understood correctly debugging software is going to need OpenOCD support and that is coming Q2/2019 for Pulpissimo. Right? 

Br,
Akim

Hello, 

I tried to run the openMP example given in pulp-rt-examples repository. But the simulation gets stuck at the rt_cluster_call(..); function in the test.c file. 

I have tried running Hello and Coremark examples for the same platform and they work perfectly. 

In order to find out that it gets at stuck at the rt_cluster_call, I put print statements before and after the function call. The modified "test.c" code is attached below. And the output seen is also attached .

Attached Files

Thumbnail(s)
           

Hello, 

I have synthesised a particular IP of the pulp system for  ASIC using a certain compiler. Now I want to re-insert the synthesised netlist into the system and perform a post-synthesis simulation for verification. How do I go about with this?

From what I understand, when a certain simulation for say hello example (given under pulp-rt-examples) is run, all the IPS are being fetched directly from the git-hub repository instead from the locally cloned repository IP folder. Is my understanding correct?

How do I add my own changes to the exisiting IP and still run an example simulation ?


Thanks!


Regards,
Athena

Hi,

is there a bug in latest PULP-SDK make script?

When I am entering: make -all    
it gives an error after running a while

sdk:pulp-rt:build (pulpissimo@config_file=chips/pulpissimo/pulpissimo.json): make build install
make[1]: Entering directory `/home/mijuna/pulp-sdk/runtime/pulp-rt'
plpflags gen  --output-dir=/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo --makefile=/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/config.mk  --property=fc/archi  --property=pe/archi  --property=pulp_chip  --property=pulp_chip_family  --property=soc/cluster  --property=host/archi  --property=fc_itc  --property=udma/hyper  --property=udma  --property=udma/cpi  --property=udma/i2c/version  --property=soc/fll  --property=udma/i2s/version  --property=udma/uart  --property=event_unit/version  --property=perf_counters  --property=fll/version  --property=soc/spi_master  --property=soc/apb_uart  --property=padframe/version  --property=udma/spim  --property=udma/spim/version  --property=gpio/version  --property=rtc  --property=udma/archi  --property=soc_eu/version  --property=compiler  --property=rtc/version  --lib=rt  --lib=omp  --lib=rtio  --lib=bench
plpconf --input=pulpissimo@config_file=chips/pulpissimo/pulpissimo.json  --config=platform=rtl  --config=**/rt/type=pulp-rt --output=/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/config.json
/home/mijuna/riscv-gnu-toolchain/bin/riscv32-unknown-elf-gcc  -march=rv32imfcxpulpv2 -mfdiv -D__riscv__ -D__RT_USE_IO=1 -Os -g -fno-jump-tables -Werror -fno-tree-loop-distribute-patterns  -Wextra -Wall -Wno-unused-parameter -Wno-unused-variable -Wno-unused-function -Wundef -fdata-sections -ffunction-sections -I/home/mijuna/pulp-sdk/pkg/sdk/dev/install/include/io -I/home/mijuna/pulp-sdk/pkg/sdk/dev/install/include -include /home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/fc_config.h    -MMD -MP -c kernel/init.c -o /home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/rt/fc/kernel/init.o
cc1: error: -march=rv32imfcxpulpv2: unsupported ISA substring 'xpulpv2'
make[1]: *** [/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/rt/fc/kernel/init.o] Error 1
make[1]: Leaving directory `/home/mijuna/pulp-sdk/runtime/pulp-rt'
Reached EOF with exit status 2
FATAL ERROR: the command 'build' has failed
make: *** [all] Error 255

Hello !

I want to synthesis the pulp SoC for 65 nm ASIC technology. Given that I have the Synopsys Compiler available is there a guide as to how proper synthesis of the pulp (with 8 RI5CY) cores can be carried out on the such that the hierarchy of the system is properly maintained during optimizations. 

Is there some example script available to direct the Synopsys compiler (or some other compiler) to perform proper synthesis. 
The final goal is to be able to perform power measurements on the synthesised design. Also, is this power analysis possible with the given repository of the pulp project on github?

Hello,

We installed the SDK and the toolchain on our Linux server and have QuestaSim-64 v10.0c
 installed.
When trying to generate the PULPissimo RTL platform I am getting the following error message during the build 'phase':

** Error: ../ips/common_cells/src/stream_mux.sv(18): near "localparam": syntax error, unexpected localparam
** Error: ../ips/common_cells/src/stream_demux.sv(20): near "localparam": syntax error, unexpected localparam
** Error: ../ips/common_cells/src/popcount.sv(21): near "localparam": syntax error, unexpected localparam
make[2]: *** [modelsim_libs/common_cells_lib/common_cells_all.vmake] Error 2
make[1]: *** [build] Error 2
make: *** [build] Error 2

Do you have any clue what can be the reason for this error?

Thanks,
Ido

On the github platform for PULP, under pulp-rt-examples repository the coremark benchmark has been given. 

This benchmark runs for platforms like the single-core platform PULPissimo as well as the PULP (8 core platform). 

However, in both cases I have inferred that the platforms are running at a frequency of 100 MHz. 

For instance this is the output obtained for the Pulpissimo with zero riscy core:

[TB]          30495473188 - Triggering fetch enable
# [TRACER] Output filename is: trace_core_1f_0.log
# [dbg_if_soc] WRITE32 burst @1a104008 for           4 bytes.
# [TB]          30509373188 - Waiting for end of computation
# [STDOUT-CL31_PE0] 2K performance run parameters for coremark.
# [STDOUT-CL31_PE0] CoreMark Size    : 666
# [STDOUT-CL31_PE0] Total ticks      : 535261
# [STDOUT-CL31_PE0] Total time (usecs): 5352
# [STDOUT-CL31_PE0] Iterations/Sec   : 186
# [STDOUT-CL31_PE0] ERROR! Must execute for at least 10 secs for a valid result!
# [STDOUT-CL31_PE0] Iterations       : 1
# [STDOUT-CL31_PE0] Compiler version : na
# [STDOUT-CL31_PE0] Compiler flags   : na
# [STDOUT-CL31_PE0] Memory location  : STATIC
# [STDOUT-CL31_PE0] seedcrc          : 0xe9f5
# [STDOUT-CL31_PE0] [0]crclist       : 0xe714
# [STDOUT-CL31_PE0] [0]crcmatrix     : 0x1fd7
# [STDOUT-CL31_PE0] [0]crcstate      : 0x8e3a
# [STDOUT-CL31_PE0] [0]crcfinal      : 0xe714
# [STDOUT-CL31_PE0] Correct operation validated. See README.md for run and reporting rules.
# [STDOUT-CL31_PE0] CoreMark 1.0 : 186 / na na / STATIC
# [TB]          45796773188 - Received status core: 0x00000000
# ** Note: $stop    : /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv(679)
#    Time: 45796773188 ps  Iteration: 0  Instance: /tb_pulp
# Break at /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv line 679
# Stopped at /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv line 679
# End time: 14:51:20 on Feb 05,2019, Elapsed time: 0:05:38
# Errors: 0, Warnings: 15


From the total time taken and the total ticks fields, it can be deduced that the platform is running at a speed of 100 MHz. 

How was this frequency chosen?

Also, is there a way to change this frequency from the coremark.patch file (or any other file for that matter) that has been given with the coremark folder under pulp-rt-examples. 

Another interesting result of running the coremark example was that I obatined the same performance numbers (as listed above) for PULP and PULPissimo (with RISCY core). Does this mean that when coremark is running on PULP it is just giving the performance number of the core and the not the entire architecture? or How to interpret these values after running the coremark. Is it only evaluating the performance of a single core regardless of the platform?