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  waves
Posted by: mahalakshmir.ma - 11-29-2019, 10:28 AM - Forum: PULP General questions - Replies (1)

hi

How to see waveforms in questasim while running the given testcases. I tried to add the signals to waveform window, but I am not able to do it. Is there any command available?.

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  Problem installing PULP-SDK
Posted by: jmmarostegui - 11-27-2019, 12:49 PM - Forum: PULP General questions - Replies (7)

Hello,

I'm trying to install PULP-SDK following the instructions provided in GitHub, but I get an error I can't understand and for which I haven't found any solution.

I'm starting from a clean Ubuntu 16.04 install, and the sequence of steps I follow (first I install the riscv gnu toolchain and then the PULP SDK) is:

1 - sudo -s

2 - apt install git python3-pip python-pip gawk texinfo libgmp-dev libmpfr-dev libmpc-dev swig3.0 libjpeg-dev lsb-core doxygen python-sphinx sox graphicsmagick-libmagick-dev-compat libsdl2-dev libswitch-perl libftdi1-dev cmake scons libsndfile1-dev

3 - pip3 install artifactory twisted prettytable sqlalchemy pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

4 - sudo pip2 install configparser

5 - cd /opt

6 - mkdir riscv

7 - cd riscv

8 - git clone https://github.com/pulp-platform/pulp-ri...-toolchain

9 - cd pulp-riscv-gnu-toolchain

10 - git submodule update --init --recursive

11 - apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev

12 - export PATH=$PATH:/opt/riscv/bin

13 - ./configure --prefix=/opt/riscv --with-arch=rv32imc --with-cmodel=medlow --enable-multilib

14 - make

15 - export PULP_RISCV_GCC_TOOLCHAIN=/opt/riscv

16 - export VSIM_PATH=/opt/riscv/pulpissimo/sim

17 - cd ..

18 - git clone https://github.com/pulp-platform/pulp-sdk.git -b master

19 - cd pulp-sdk

20 - source configs/pulpissimo.sh

21 - make all

After this last command I get the following error:

Configuring Pulp project at /opt/riscv/pulp-sdk
Traceback (most recent call last):
  File "./pulp-tools/bin/plpbuild", line 3, in <module>
    import plptools as plp
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plptools.py", line 27, in <module>
    from plpobjects import *
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plpobjects.py", line 32, in <module>
    from openpyxl import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/__init__.py", line 6, in <module>
    from openpyxl.workbook import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/workbook/__init__.py", line 4, in <module>
    from .workbook import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/workbook/workbook.py", line 7, in <module>
    from openpyxl.worksheet.worksheet import Worksheet
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/worksheet/worksheet.py", line 392
    return f"{get_column_letter(min_col)}{min_row}:{get_column_letter(max_col)}{max_row}"
                                                                                        ^
SyntaxError: invalid syntax
Makefile:6: recipe for target 'all' failed
make: *** [all] Error 1

Following the instructions provided in GitHub I check the versions of both python and pip. What I get is:

root@VBox:/opt/riscv/pulp-sdk# pip --version
pip 19.3.1 from /usr/local/lib/python2.7/dist-packages/pip (python 2.7)
root@VBox:/opt/riscv/pulp-sdk# python3 --version
Python 3.5.2

Then I execute the commands suggested in GitHub:

python3 -m pip install --upgrade pip
python3 -m pip install artifactory twisted prettytable sqlalchemy pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

However, when I run again 'make all' I get the same error. Since after looking for a solution I haven't found any clue how to fix it, could you provide me any hint to overcome this problem? Thank you very much in advance for your help.

Best regards,

Manuel

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  GDB Debugging with JTAG on Ariane
Posted by: jthoma - 11-26-2019, 09:58 AM - Forum: PULP General questions - Replies (4)

Hi,

I have problems using the JTAG debugging connection with GDB for the Ariane Softcore. The Genesys 2 Board is connected to my PC via JTAG. I have OpenOCD with RISC-V support  installed on my machine and it seems to connect just fine:

Code:
~/Desktop/ariane $ openocd -f fpga/ariane.cfg
Open On-Chip Debugger 0.10.0+dev-00828-gde00906eb (2019-11-25-14:04)
Licensed under GNU GPL v2
For bug reports, read
       http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (<invalid>), part: 0x0000, ver: 0x0)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 1 harts
Info :  hart 0: XLEN=64, misa=0x800000000014112d
Info : Listening on port 3333 for gdb connections
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333

This does look quite similar to the output in the Ariane git with the exception of this line:
Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (<invalid>), part: 0x0000, ver: 0x0)

I don't know whether this causes the problem or not gdb seems to connect just fine.

Okay, now to the actual problem. If I connect gdb and load the binary (a simple hello world), the PC points to _start. Unfortunately, _start contains loads of unimp instructions and does not redirect the program flow to the main function. Thus, if I do a continue, nothing happens. Same goes for break main etc. as the main function is apparently never called. See the GDB output below:

Code:
Reading symbols from ./out...
(gdb) target extended-remote :3333
Remote debugging using :3333
0x000000000001071c in _vfprintf_r ()
(gdb) load
Loading section .text, size 0xbd2c lma 0x100b0
Loading section .rodata, size 0xd08 lma 0x1bde0
Loading section .eh_frame, size 0x4 lma 0x1dae8
Loading section .init_array, size 0x10 lma 0x1daf0
Loading section .fini_array, size 0x8 lma 0x1db00
Loading section .data, size 0x1100 lma 0x1db08
Loading section .sdata, size 0x58 lma 0x1ec08
Start address 0x100c6, load size 56232
Transfer rate: 47 KB/sec, 5623 bytes/write.
(gdb) where
#0  0x00000000000100c6 in _start ()
(gdb) x/5i $pc
=> 0x100c6 <_start>:    unimp
  0x100c8 <_start+2>:  unimp
  0x100ca <_start+4>:  unimp
  0x100cc <_start+6>:  unimp
  0x100ce <_start+8>:  unimp
(gdb) cont
Continuing.

Interestingly, if I disassemble the _start function in a local GDB Session, it looks like this: 
Code:
(gdb) disassemble _start
Dump of assembler code for function _start:
  0x00000000000100c6 <+0>:     auipc   gp,0xe
  0x00000000000100ca <+4>:     addi    gp,gp,1066 # 0x1e4f0 <__malloc_av_+248>
  0x00000000000100ce <+8>:     addi    a0,gp,1904
  0x00000000000100d2 <+12>:    auipc   a2,0xf
  0x00000000000100d6 <+16>:    addi    a2,a2,-994 # 0x1ecf0
  0x00000000000100da <+20>:    sub     a2,a2,a0
  0x00000000000100dc <+22>:    li      a1,0
  0x00000000000100de <+24>:    jal     ra,0x1020c <memset>
  0x00000000000100e2 <+28>:    auipc   a0,0x9
  0x00000000000100e6 <+32>:    addi    a0,a0,-1238 # 0x18c0c <atexit>
  0x00000000000100ea <+36>:    beqz    a0,0x100f8 <_start+50>
  0x00000000000100ec <+38>:    auipc   a0,0x2
  0x00000000000100f0 <+42>:    addi    a0,a0,1108 # 0x12540 <__libc_fini_array>
  0x00000000000100f4 <+46>:    jal     ra,0x18c0c <atexit>
  0x00000000000100f8 <+50>:    jal     ra,0x101a2 <__libc_init_array>
  0x00000000000100fc <+54>:    lw      a0,0(sp)
  0x00000000000100fe <+56>:    addi    a1,sp,8
  0x0000000000010100 <+58>:    li      a2,0
  0x0000000000010102 <+60>:    jal     ra,0x1015c <main>
  0x0000000000010106 <+64>:    j       0x10184 <exit>

Am I missing something here? Do I need an extra GDB command to load the _start funtion or does it have to be compiled in a specific way? I compiled the binary with riscv64-unknown-elf-gcc test.c -o out and also tried adding -ffreestanding.

Thank you!
- Jan

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  HEX Files
Posted by: mahalakshmir.ma - 11-25-2019, 07:10 AM - Forum: PULP General questions - Replies (5)

Hi,

In PULPino environment there are some HEX Files getting generated while i tried to run testcase. So my query is where the conversion from C to HEX file is taking place (code & path). 

thanks in advance.


(11-25-2019, 07:10 AM)mahalakshmir.ma Wrote: Hi,

In PULPino environment there are some HEX Files getting generated while i tried to run testcase. So my query is where the conversion from C to HEX file is taking place (code & path). 

thanks in advance.

PULPino environment - https://github.com/pulp-platform/pulpino

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  questasim
Posted by: mahalakshmir.ma - 11-22-2019, 01:08 PM - Forum: PULP General questions - Replies (4)

hi,
 while simulating GPIO in questasim I am getting following error.
please tell me why this occurs and how to resolve it.


thankyou

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  PULPissimo Synthesis and Clock Distribution
Posted by: AhmedZaky - 11-20-2019, 06:55 AM - Forum: PULP General questions - Replies (1)

Hi all, 

First of all, thanks a lot for your help and support.

I was wondering if there is a synthesis - clean version of PULPissimo that's already released to the public. If not, is there any document / way to understand how the clock the distribution is going ? 

What I understand, correct me if I am wrong, that in the case of: 

1- FPGA, u r using a reference clock of 200 MHz to generate two internal clocks by divisions: A- Soc_clk = 20Mhz , B- periph_clk = 10Mhz.

2- In case of the RTL simulation, you r feeding from the TB a reference clock of ~ 32KHz and somehow, using DCO, FLL generating two clocks soc_clk = periph_clk = 17.5 MHz. 

If I am correct, are this on-chip clock generation modules synthesizable? Or they should be mapped to IPs in the PDK ? 

--------- 

Assuming that I want to drive the whole chip using the external clock, is it save to just remove all the " fll, DCO.. etc" modules and pass the signal through the modules to all the system components ? I mean the PAD_xtal_clk, pass it for the fc_subsystem, l2_memory .. etc and the system can work on that clock ? I already did simulation and it worked, but I am making sue that I didn't miss anything as I didn't test the system exhaustively. 

Thanks in advance.

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  Library Files
Posted by: mahalakshmir.ma - 11-15-2019, 10:19 AM - Forum: PULP General questions - Replies (6)

Hi,

I tried to include a new peripheral (PWM) into the PULPino environment, where can I get the library files for that peripheral or it will be auto generated.

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  Pulpissimo make error when making hello example
Posted by: bunohdwnl - 11-14-2019, 02:36 AM - Forum: PULP General questions - Replies (3)

Hello! I do the flow according to the Pulpissimo's README.md. But I meet a make error when I execute  the flow at the step "Downloading and running tests ".I change directory to  pulp-rt-examples/hello, and execute make clean all run ,then a "No Such File or Directory" error appears. I cat the Makefile,maybe the PULP_SDK_HOME is undefined. Do I need to set the PULP_SDK_HOME in my .bashrc  manually?

Code:
[jiaopy@localhost Jproject]$ cd pulp-rt-examples/hello/
[jiaopy@localhost hello]$ make clean all run
Makefile:6: /install/rules/pulp_rt.mk: No such file or directory
make: *** No rule to make target `/install/rules/pulp_rt.mk'.  Stop.
[jiaopy@localhost hello]$ cat Makefile
PULP_APP = test
PULP_APP_FC_SRCS = test.c
PULP_APP_HOST_SRCS = test.c
PULP_CFLAGS = -O3 -g
include $(PULP_SDK_HOME)/install/rules/pulp_rt.mk

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Question errors on building Linux cross-compiler
Posted by: mapletree - 11-12-2019, 09:16 PM - Forum: PULP General questions - Replies (5)

   
[attachment=15][attachment=15]
Hi,
I got some errors when build Linux cross-compiler with the following command:

Code:
./configure --prefix=/opt/riscv
make linux

The errors message is shown in the attached screenshot.
Anyone has an idea how to fix it?

Thanks!

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  Set defines of modules
Posted by: LPLA - 11-12-2019, 04:12 PM - Forum: PULP General questions - Replies (2)

Hello,

throughout the code you can find things like:

Code:
`ifdef QUENTIN_SCM
...
`endif

or

Code:
`ifndef PULP_FPGA_EMUL
...                              
`else
...
`endif

and there are two things about this that i just couldn't figure out.

First: Where are those defines? Let's say i want to use Quentin, where would i put `define QUENTIN_SCM (assuming this is the correct syntax).

Second: Assume i am having three different modules for multiplication mul1, mul2, mul3.
Every module has additional inputs if you want to do floating point multiplication.
This is handled by:
Code:
`ifdef FP_ENABLE
... (additional inputs)
`endif


I tested all three modules with Questasim using a testbench and created a .do file for them.
Now inside my .do file i have the following command:
Code:
set ms [concat mul1 mul2 mul3]
foreach m ${ms} {
  vlog -64 +define+FP_ENABLE ../multis/${m}/rtl/${m}.sv
}


If i now try to use my modules somewhere in PULPissimo i get some errors from my makefile that tell me some ports of the module are missing.
Basically the above command tells the modules mul1, mul2, mul3 that FP_ENABLE is defined and therefore the additional ports are instantiated.
Unfortunately i don't know how to use the same idea when trying to instantiate a mul-module in PULPissimo.
It is important to note that i don't want to change any line of code in the mul-modules!
Does anyone know a way how to tell the modules its defines just like the above command does?

Thank you.
LPLA

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