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  Does Pulpissimo already contain VCC & GND pins?
Posted by: traVc - 01-03-2021, 06:16 PM - Forum: PULP General questions - Replies (3)

I was wondering whether Pulpissimo already contains VCC & GND (power supply) pins or if those have to be added for ASIC design?

If they have to be added - what would be the easiest way to do so?

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  [Vivado] behavioural simulation won't start
Posted by: andrea.spitale - 12-10-2020, 11:14 AM - Forum: PULP General questions - Replies (7)

Hi there!
I'm posting here as I am having some trouble with setting up PULPissimo to be behaviourally simulated (i.e. pre synthesis) on Vivado. In order to do so, I've cloned the PULPissimo repository, then run the update ips script and finally loaded all files from ips and rtl folders into vivado project. I'll list the issues I've encountered, together with vivado logs describing the errors and warning the software detected, considering I am running a fully licensed 2020.2 version under Linux.

1) i've a huge issue with "include" files, that is the files referred by `include directives. The vivado log referring to this issue is the one named "vivado_include.log".
1.1) Initially I managed to fix some of these errors by adding the paths to the folders containing those files in "Verilog Include Files Search Paths", which is a setting that can be found by going through Project Manager -> Settings -> General(and Simulation) -> Verilog Options, but this means adding one path for every "include" error the compiler detects, so it requires a lot of work. Moreover it doesn't seem to be always working, as it didn't fix the problem when I created a new project and the log content was the same as "vivado_include.log".

2) I created another project, this time copying and including all .sv, .svh, .v files from ips and rtl PULPissimo folders, so all files are in the same folder. I had to modify the `include directives of "fpnew" IP files in order to have correct `include paths. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv, as the compiler was not able to recognize "timeunit" and "timeprecision" keywords, although it should. Then, using xilinx related scripts inside "fpga/zcu102" folder as a guideline, I created the Xilinx IPs PULPissimo requires, that is two BRAMs and two clock generators, named xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. Once I ran the behavioural simulation process, the compile phase went fine, but then the elaborate one was stopped with errors listed in "vivado_elaborate.log" file. I have to say I also read some warnings during compile phase, which details are again listed in "vivado_elaborate.log".

3) I created a new project, importing all files from ip and rtl folders. I've set some of the files referred by `include directives as "verilog header" from the files properties. Then I copied the registers.svh file inside "common_cells" folder of FPNEW ip, as the compiler was not able to find it. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv. However I still encountered errors after running behavioural simulation process, one of them referring to file riscv_alu.sv, with compiler indicating that  "riscv_defines" packanot being declared.ge has not been declared. The log of this operation is inside "vivado_third_attempt.log".

All .log files are inside the attached "vivado_error_logs.zip" file.

Hope everything is clear. Thank you for your time!

Attached Files
.zip   vivado_errors_logs.zip (Size: 6.6 KB / Downloads: 0)
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  How to solve the problem of missing modules “pulpissimo”?
Posted by: LanXu - 12-08-2020, 09:05 AM - Forum: PULP General questions - Replies (1)

   I want run openPULP project in zcu104 FPGA.After i ran update_ips script,i make  zcu104 under the path ../workspace/pulp/pulp/fpga.The following error occurred:
  ERROR: [Synth 8-439] module 'pulpissimo' not found [../workspace/pulp/pulp/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v:99]
   I want to know how to fix this problem,and Is it necessary to build the SDK?  Can the SDK be built on the centos7 system?and how?

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  Help to run Hello Example
Posted by: igor.lima - 12-01-2020, 08:05 PM - Forum: PULP General questions - Replies (4)


I'm new in community, i'd like some help!

I'm trying to run the Hello example from "https://github.com/pulp-platform/pulp-rt-examples" in my Nexys Video FPGA using the bitstream of Pulpissimo.

Until now i'm just following the instructions from README.md file from "https://github.com/pulp-platform/pulpissimo".

I had download and install the Toolchain from pulp-riscv-gnu-toolchain as "Newlib", could someone confirm that it is not necessary install the "Linux" version of this toolchain?

Then i installed the Standard Pulp SDK from "https://github.com/pulp-platform/pulp-sdk/#standard-sdk-build"

I had some issues following the steps, most of them are related with missing steps, like configuring bashrc or some ambient variable, but i was able to solve all of them i believe. I miss some kind of step-by-step, from rtl to running example on FPGA, is it possible create something like that? I think it could be done as a new Thread in forum for the communty, it could help a lot.

I was able to generate the bitstream of Pulpissimo and configure it in Nexys Video FPGA using the JTAG-USB connection. When i run the specific OpenOCD from Pulp-SDK, the OpenOCD is able to identify the Pulpissimo processor in FPGA.

Then i compiled the Hello Example after adding the two weakly defined variables as suggested to configure core and peripherics frequencies. It was compiled with success, the ELF file was properly generate in the build directory.

My problem happen when i had try to use GDB with ELF file to load it to L2 memory of Pulpissimo, the connection between the GDB and OpenOCD looks fine, when i use the Load command it copy the elf file to memory it looks to work fine too, but when i use the Continue command it stops and never end the execution, but it print some kind of assembly commands like;
# j    1c0080ec <__rt_illegal_instr>

So i did the check with gcc in the ELF file to check the Assembly, as suspected it was printing the assembly that has some kind of error i believe, the first piece of assembly code is like that;

test:     file format elf32-littleriscv

Disassembly of section .vectors:

1c008000 <__irq_vector_base>:
1c008000:    0ec0006f              j    1c0080ec <__rt_illegal_instr>
1c008004:    0900006f              j    1c008094 <__rt_no_irq_handler>
1c008008:    08c0006f              j    1c008094 <__rt_no_irq_handler>
1c00800c:    0880006f              j    1c008094 <__rt_no_irq_handler>
1c008010:    0840006f              j    1c008094 <__rt_no_irq_handler>
1c008014:    0800006f              j    1c008094 <__rt_no_irq_handler>
1c008018:    07c0006f              j    1c008094 <__rt_no_irq_handler>
1c00801c:    0780006f              j    1c008094 <__rt_no_irq_handler>
1c008020:    0740006f              j    1c008094 <__rt_no_irq_handler>
1c008024:    0700006f              j    1c008094 <__rt_no_irq_handler>
1c008028:    06c0006f              j    1c008094 <__rt_no_irq_handler>
1c00802c:    0680006f              j    1c008094 <__rt_no_irq_handler>
1c008030:    0640006f              j    1c008094 <__rt_no_irq_handler>
1c008034:    0600006f              j    1c008094 <__rt_no_irq_handler>
1c008038:    05c0006f              j    1c008094 <__rt_no_irq_handler>
1c00803c:    0580006f              j    1c008094 <__rt_no_irq_handler>
1c008040:    0540006f              j    1c008094 <__rt_no_irq_handler>
1c008044:    0500006f              j    1c008094 <__rt_no_irq_handler>
1c008048:    04c0006f              j    1c008094 <__rt_no_irq_handler>
1c00804c:    0480006f              j    1c008094 <__rt_no_irq_handler>
1c008050:    0440006f              j    1c008094 <__rt_no_irq_handler>
1c008054:    0400006f              j    1c008094 <__rt_no_irq_handler>
1c008058:    03c0006f              j    1c008094 <__rt_no_irq_handler>
1c00805c:    0380006f              j    1c008094 <__rt_no_irq_handler>
1c008060:    0340006f              j    1c008094 <__rt_no_irq_handler>
1c008064:    0300006f              j    1c008094 <__rt_no_irq_handler>
1c008068:    02c0006f              j    1c008094 <__rt_no_irq_handler>
1c00806c:    0280006f              j    1c008094 <__rt_no_irq_handler>
1c008070:    0240006f              j    1c008094 <__rt_no_irq_handler>
1c008074:    0200006f              j    1c008094 <__rt_no_irq_handler>
1c008078:    01c0006f              j    1c008094 <__rt_no_irq_handler>
1c00807c:    0180006f              j    1c008094 <__rt_no_irq_handler>

1c008080 <_start>:
1c008080:    0200006f              j    1c0080a0 <_entry>
1c008084:    0680006f              j    1c0080ec <__rt_illegal_instr>

1c008090 <__rt_debug_struct_ptr>:
1c008090:    0cf4                    addi    a3,sp,604
1c008092:    1c00                    addi    s0,sp,560

1c008094 <__rt_no_irq_handler>:
1c008094:    0000006f              j    1c008094 <__rt_no_irq_handler>

1c008098 <__rt_semihosting_call>:
1c008098:    00100073              ebreak
1c00809c:    00008067              ret

Disassembly of section .text:

1c0080a0 <_entry>:
1c0080a0:    7a101073              csrw    pcmr,zero
1c0080a4:    ffff9297              auipc    t0,0xffff9
1c0080a8:    d2c28293              addi    t0,t0,-724 # 1c000dd0 <_bss_start>
1c0080ac:    ffff9317              auipc    t1,0xffff9
1c0080b0:    e0030313              addi    t1,t1,-512 # 1c000eac <__l2_priv0_end>
1c0080b4:    0002a023              sw    zero,0(t0)
1c0080b8:    0291                    addi    t0,t0,4
1c0080ba:    fe62ede3              bltu    t0,t1,1c0080b4 <_entry+0x14>
1c0080be:    ffff9117              auipc    sp,0xffff9
1c0080c2:    c0210113              addi    sp,sp,-1022 # 1c000cc0 <stack>
1c0080c6:    292000ef              jal    ra,1c008358 <__rt_init>
1c0080ca:    00000513              li    a0,0
1c0080ce:    00000593              li    a1,0
1c0080d2:    00000397              auipc    t2,0x0
1c0080d6:    26438393              addi    t2,t2,612 # 1c008336 <main>
1c0080da:    000380e7              jalr    t2
1c0080de:    842a                    mv    s0,a0
1c0080e0:    350000ef              jal    ra,1c008430 <__rt_deinit>
1c0080e4:    8522                    mv    a0,s0
1c0080e6:    330010ef              jal    ra,1c009416 <exit>

1c0080ea <_fini>:
1c0080ea:    8082                    ret

1c0080ec <__rt_illegal_instr>:
1c0080ec:    fe112e23              sw    ra,-4(sp)
1c0080f0:    fea12c23              sw    a0,-8(sp)
1c0080f4:    00000517              auipc    a0,0x0
1c0080f8:    3ba50513              addi    a0,a0,954 # 1c0084ae <__rt_handle_illegal_instr>
1c0080fc:    010000ef              jal    ra,1c00810c <__rt_call_c_function>
1c008100:    ffc12083              lw    ra,-4(sp)
1c008104:    ff812503              lw    a0,-8(sp)
1c008108:    30200073              mret

1c00810c <__rt_call_c_function>:
1c00810c:    7119                    addi    sp,sp,-128
1c00810e:    c006                    sw    ra,0(sp)
1c008110:    c20e                    sw    gp,4(sp)
1c008112:    c412                    sw    tp,8(sp)
1c008114:    c616                    sw    t0,12(sp)

What could i have done to generate some kind of illegal instruction during the compiling process? is it not wrong after all?

When i use the gdb command "disas" it print the C code properly...

If you need any more information, just ask

Any help will be very helpful

Best Regards, Igor Ruschi

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  Resource Utilization of PULPino/PULPissimo in FPGA
Posted by: Mwind - 11-20-2020, 08:06 AM - Forum: PULP General questions - Replies (4)


I am currently evaluating the use of RISC-V processors in FPGAs. Has anyone implemented a PULPino or PULPissimo on an FPGA and can you make rough statements about the resource usage?

I would appreciate any information. Thanks in advance.

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  Is there an IDE?
Posted by: nikolas - 11-18-2020, 04:04 PM - Forum: PULP General questions - Replies (2)

Hi there 

I was wondering if there is any opportunity to work with the Eclipse IDE to program and debug the PULPissimo that is running on a NEXYS 4 board?

Or is there any other IDE, that would be able to do that?

Would really like to find an easier way to work with PULPissimo than compiling, downloading and debugging from the command line.

Thank you very much for all kind of ideas.

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  Building an RTL simulation platform Error
Posted by: RiscV - 11-03-2020, 10:24 AM - Forum: PULP General questions - Replies (1)

I followed the readme file of pulpissimo  for building an RTL simulation platform. After the following steps

source setup/vsim.sh

make build

I am getting error like this

make -C ../rtl/tb/remote_bitbang all
make[2]: Entering directory '/opt/pulpissimo/rtl/tb/remote_bitbang'
cc -MT remote_bitbang.o -MMD -MP -MF ./.d/remote_bitbang.Td -std=gnu11 -fno-strict-aliasing -Wall -Wextra -Wno-missing-field-initializers -Wno-unused-function -Wno-missing-braces -O2 -g -march=native -DENABLE_LOGGING -DNDEBUG -fPIC -I./  \
    -c  remote_bitbang.c -o remote_bitbang.o
ld -shared -E --exclude-libs ALL -o librbs.so  \
    remote_bitbang.o sim_jtag.o
make[2]: Leaving directory '/opt/pulpissimo/rtl/tb/remote_bitbang'
/usr/bin/env: ‘tclsh’: No such file or directory
Makefile:37: recipe for target 'opt' failed
make[1]: *** [opt] Error 127
make[1]: Leaving directory '/opt/pulpissimo/sim'
Makefile:47: recipe for target 'build' failed
make: *** [build] Error 2

 I am using ModelSim - Intel FPGA Edition 20.3 (includes Starter Edition).  Please help me ..

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  PULPissimo FLL bypass
Posted by: Supra - 10-30-2020, 03:33 PM - Forum: PULP General questions - Replies (5)

Hello everyone,
Could someone please help me bypass the FLL logic ? I want to use an external clock for my design.
At the moment, I have removed the gf22_FLL instances and tried to connect soc_clk and per_clk directly to ref_clk.
Could anyone please share their experience of bypassing the FLL ? How did you handle the rest of the logic present in soc_clk_rst_gen.sv file ?
With this, I get error captured in the attachment. 


Attached Files Thumbnail(s)
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  Pulpissimo- errors during FPGA synthesis.
Posted by: plumerai - 09-25-2020, 04:23 PM - Forum: PULP General questions - Replies (2)

I am trying to synthesize Pulpissimo with Vivado 2019.2 for nexys A7-100. I get the following errors:

[Place 30-69] Instance i_pulpissimo/pad_frame_i/padinst_bootsel/iobuf_i/IBUF (IBUF driven by I/O terminal i_pulpissimo/pad_frame_i/padinst_bootsel/iobuf_i/IO) is unplaced after IO placer
[Place 30-68] Instance i_pulpissimo/pad_frame_i/padinst_bootsel/iobuf_i/IBUF (IBUF) is not placed
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

I didn't modify a bit after cloning the repo.

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  Adding custom instructions into RI5CY core
Posted by: plumerai - 09-25-2020, 09:04 AM - Forum: PULP General questions - Replies (4)

We are currently evaluating the RI5CY core for our project and the possibility of adding custom instructions is important for us. Some other cores (Sifive E31, Vexriscv) have simple and documented ways to do this, but I couldn't find the information about RI5CY. HWPEs are great but we may need a true custom instruction support for our needs.

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