When I use plp_mkflash in pulp-sdk/tools/runner/bin to make
flash.bin, the plp_mlflash tools display there is no module named “runner”
How can I solve it? I have build sdk successful.

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I am stacked in installing the pulp-sdk.
First of all I have succesfully installed the pulp-rsicv-gnu-toolchain following the instruction on github https://github.com/pulp-platform/pulp-ri...-toolchain .
I performed the following step (I omit the part in which I install all the dependencies) :

1. $ git clone --recursive https://github.com/pulp-platform/pulp-ri...-toolchain

2. $ cd pulp-riscv-gnu-toolchain

3. $ export PATH=/opt/riscv/bin:$PATH

4. $ ./configure --prefix=/opt/riscv --with-arch=rv32imc --with-cmodel=medlow --
enable-multilib

5. $ make

Then I followed the instruction on github for what concern pulp-sdk https://github.com/pulp-platform/pulp-sdk .
I performed the following step (I omit the part in which I install all the dependencies) :

1. $ git clone https://github.com/pulp-platform/pulp-sdk

2. $ export PULP_RISCV_GCC_TOOLCHAIN=/opt/riscv

3. $ cd pulp-sdk

4. $ source configs/pulp-open.sh

5. $ make build

At step n°5 i have the following error:

Quote:cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo \

-DCMAKE_INSTALL_PREFIX=/home/luca/Desktop/Tesi/pulp-sdk/install/workstation \
-DGVSOC_MODULES="/home/luca/Desktop/Tesi/pulp-sdk/tools/gvsoc/common;/home/luca/Desktop/Tesi/pulp-sdk/tools/gvsoc/pulp" \
-DGVSOC_TARGETS=pulp-open
Re-run cmake no build system arguments
CMake Error: The source directory "/home/luca/Desktop/Tesi/pulp-sdk/build" does not exist.
Specify --help for usage, or press the help button on the CMake GUI.
Makefile:26: recipe for target 'build' failed
make: *** [build] Error 1

Hi, I'm trying run some tests about qspi in Genesy 2 broad but I have some problems. When run simulation with flash model, everything is good so I program it to my Kit. In genesys 2 have a qspi flash so I want to use it like a peripheral. In this reference, signals of qspi can connect via port in XDC file, expect qspi_sck. It must be connected via STARTUPE2. When I do so, it runs incorrectly. My test run through all code line but wave form in ocilloscope is different from Questasim.  Have anyone met this problem like that before?
Thanks

We are trying to boot the PULP project whose original 8 riscv cores(ri5cy) have been replaced by 2 simd cores with 128bits datapath customized by us. We also replace the original HWPE with our customized systolic array. And we have successfully run RTL and Netlist systhesized by Design Compiler simulation. Now we are trying to boot it on our FPGA, but it seems we can boot the fc core(fabric controller) but fail to boot the cluster.
    We try to use gdb and openocd to debug step by step. It seems when the fc step into the cluster starting part, it's stuck. So we want to use gdb to connect our simd cores whose hart id are 0 and 1(the original 8 cores' hart id are 0-7, fc's hart id is 992(0x3e0)，and we edit our jlink configuration file and add extra target create to trace the simd cores. But openocd reports it can't halt the core with id 0 and 1.
    So here are my questions:
    1、We would like to start a customized cluster. Are there any particular considerations or other methods that could help us with debugging? We welcome any suggestions you might have.
    2、For this heterogeneous kind of multicore system (one FC and two SIMD cores), how should we perform step-by-step debugging using GDB+OpenOCD? I would like to trace the FC and SIMD cores to see where exactly something went wrong. Or in other words, in the original PULP system, how should we go about debugging the 8 cores in the cluster and the FC core simultaneously?

Here's the jlink configuration file, we add extra target create to trace cores with id 0 and 1 but failed. Openocd reports it can't halt them.

Hi, 

Our team is currently working on taping out the "openPulp" design. We have synthesized the design using the Synopsys Design Compiler tool and performed Static Timing Analysis (STA) using Synopsys' Primetime. We noticed some peculiarities in the timing_max_normal_path.rpt report, which can be broadly categorized as follows: 

1.  Paths from CORE[0].ex_stage to another CORE.id_stage through FPNEW_UNIT,  with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/. 
   
2.  Paths from ex_stage to id_stage, with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/. 
   
3.  Paths related to the DFFs with the hwloop_regs_i_hwlp_counter_q_reg_ prefix in the id_stage. 
   
Additionally, we observed that signals such as mult_multicycle_i in the riscv_decoder module are annotated with comments like "//multiplier taking multiple cycles," as well as the apu_singlecycle and apu_multicycle signals. 

Our question is: Should the paths mentioned above be treated as multi-cycle paths or false path during synthesis? 

We would greatly appreciate any insights or guidance on this matter. 
Thank you in advance for your assistance. 
Best regards, 
[keran]

Attached Files

  PT timing report_openPulp.pdf (Size: 796.97 KB / Downloads: 3)

Hi, 

I'm trying to edit the address access on some parts of the code cause I may have to avoid using some CUTS of the L2 ram, and I cannot change the RTL as the design was already sent for tape-out. 
I'm not familiar with Assembly, but is it possible to get the code in Assembly and change the variables addresses to use only specific banks of the RAM? So far, I got the code from the command "make dis" but I think the code is formatted for debugging purposes, is there any command to get a working assembly code from the .c file?

Thanks in advance.

Hi
I'm a semiconductor specialist solutions architect, and I'm building an open-source post-silicon (yield) analytics solution. 
I'm hoping to partner with the PULP project, looking for parties that have taped-out an open-source chip, and have STDF files we can use to build this new tool...

Does the PULP project tape out chips? Is there a possibility to collaborate here?

Thanks,

Hi, 

I'm trying to test Pulpissimo in Nexys Video FPGA, so far I can generate and load the bitstream to the FPGA, but when running OpenOCD, it shows the following error of "Debug Module did not become active. dmcontrol = 0x0"

Hello,

We are trying to get HERO running on a Xilinx ZCU102 board as per the project Readme instructions. We've got to the point of trying to boot the host processor but a kernel panic occurs afther the error: "Unable to handle kernel paging request at virtual address ffffffc078000001", as can be seen in the attached log. Chan someone shed some light on this?

The Readme instructions say that "On the first boot, change the U-Boot variables as described in issue #107", but strangely there is no "Issues" tab on the HERO Github repository so we don't know if our issue is related with that variable change.

Thank you in advance. Best regards,

Pedro Lobo.

Attached Files

  uboot-log-01.txt (Size: 13.5 KB / Downloads: 0)

Hi, 

Earlier I used SDK V1 to compile C codes to run over FPGAs, however, I used it with an older version of the RTL. Many changes have been made to the RTL and a new SDK version has been released. 

However, the new SDK doesn't have instructions on how to compile applications for FPGA targets neither I see the same directory structure as the old one.

When I used the V1 SDK to compile the application to run over the Nexys A7 using the new RTL, I faced this issue: 

Quote:19 #include <stdio.h>

20 #include <rt/rt_apt.h>

22 int __rt_fpga_fc_frequency = 10008000; // e.g. 10000800 for 10MHZ;
23 int __rt_fpga_periph_frequency = 5000000; // e.g. 5000000 for SMHZ;
24
(gdb) list

26 int main()

27 {

28 while (1) {

29 printf("Hello World!\n\r");

30 for (volatile int i=6; 1<1000008; i++);

31 }

2 return 0;

(gdb) continue

Continuing.

^c

Program received signal SIGINT, Interrupt.
0x1c009452 in __rt_exit_debug_bridge (status= -1)  at libs/i0/10.c:560
 __rt_bridge_clear_notif();