How to perform regression test when the compiler is replaced with LLVM, The compiler used by the existing regression test is GCC. I want to compile it with clang to run the regression test. Or, there are other test sets to test whether the clang compiler can correctly generate the instruction of pulp.

Hello! I'm interested in creating custom extensions to the RISC-V ISA. The goal of these extensions would be to define instructions that perform specific operations (e.g., butterfly operations, twiddle factor generation, modular arithmetic) that I can use to implement various cryptographic primitives (e.g., NTT). I would then like to measure the speedup of these cryptographic primitives with my extensions enabled vs. with my extensions disabled.

What would be the best platform to achieve this goal?

I see one possibility, which is to take the CV32E40P core and extend it with custom functional units using SystemVerilog. I'd then have to find a way to get the compiler to take advantage of the new instructions that I've defined.

While I would be comfortable using SystemVerilog, I'm more interested in exploring the design space of possible instructions rather than attempting to debug a particular hardware design. For this reason, I'm curious if an architectural simulator / instruction set simulator would be more appropriate for my needs. Does PULP offer an architectural simulator / instruction set simulator? I found GVSoC, but I'm not sure if it's what I'm looking for.

Any advice would be greatly appreciated. Thank you!

Hi,
looking at website, I see several cores have been taped out.
I'm trying to find more info in how tape out has been carried out.
Is the tape out flow fully based on the RTL of the cores (the one available on GitHub repos) or human circuit customization has been
performed ?
For example, looking at https://github.com/openhwgroup/cv32e40p core I see the register file is described at high level as a simple array.
When it comes to circuit implementation has the synthesis  had free room to decide how to translate the RF in real digital circuit or some human
customization has been carried out?

Hello, good time!

I'm going to run PULPino and i used ri5cy_gnu_toolchain for this.
But when using the ./cmake_configure.riscv.gcc.sh command, I get the following error:

C compiler identification is unknown
System unknown to cmake, create:
Platform/Linux-CXX To use this system, please send your configuration file to cmake@www.cmake.org so it can be added to cmake.
Your CMakeCache.txt file was copied to CopyOfCMakeCache.txt. Please send that file to cmake@www.cmake.org.
CMake error in CMakeLists.txt:20 (enable_language):
No CMAKE_C_COMPILER found.
Tell CMake where to find the compiler by setting the environment
"CC" variable or CMake cache entry CMAKE_C_COMPILER to full path to
Compiler or named Compiler if it is in PATH.
The configuration is incomplete, errors have occurred!
See also "/home/ali/pulpino/sw/build/CMakeFiles/CMakeOutput.log".
See also "/home/ali/pulpino/sw/build/CMakeFiles/CMakeError.log".

Also, the PATH variable related to ri5cy as below in the bashrc file. I added:
export PATH=/home/ri5cy_gnu_toolchain/install/bin:$PATH
Thanks in advance for your help!

Hello,

I'm planning to run PULPino on Ubuntu 20.04 and started at https://github.com/pulp-platform/pulpino.

Do I need to use a specific gcc to run? Can you explain the steps involved in implementing this platform?

Thanks dear friends

Hello,

I am new to RTL simulations, and I noticed that many of the PULP platforms appear to require QuestaSim in order to conduct them, but I am not too familiar with RTL environment setups. Specifically, I am currently working with HERO and Pulpissimo. 

I was wondering if anyone has any pointers or recommendations on where to look for instructions to set up a complete QuestaSim environment from scratch. The machine I am running on is CentOS 7.

Thank you very much in advance.

Can I directly use mempool code on FPGA? Or where can I get a reference to use mempool, attached with mempool github link

https://github.com/pulp-platform/mempool



Thank you in advance

crazyfly

Hi everyone,

I am new in RISC-V and I am using Pulpissimo.
Is there somewhere a tutorial of how to create new custom instructions in RISC-V?
For instance, a "mod" instruction.
What are the steps to do it?

Thank you in advance,
Theodoros

Hi, 

I'm trying to synthesize PULPissimo using Genus Synthesis Solution. But it is showing a lot of errors and warning about unsynthesizable codes on read_hdl -sv command (e.g., class declaration, @(posedge )), and some errors about attributes which in this case, after reading a bit about, I ignored when they were warnings or deleted when they were errors. 

The code was made to be synthesizable, i guess, right? The problem might be in the old version of Genus that I'm using in the server (version 16.20), but are those examples (class declaration and @(posedge)) supported in the new version of Genus? 
Also, I've defined the macros SYNTHESIS and ASIC_SYNTHESIS just in case when running read_hdl, though that didn't seem to solve any of the error showed. Are there any more macros needed for the synthesis?

I attached the log of the read_hdl command, showing all the warnings and errors. 

Thanks in advance, ivanhira.

Attached Files

  genus_log.txt (Size: 39.32 KB / Downloads: 4)

Did anybody check that the PULP platform (in general, I mean several projects) SystemVerilog compiles with Intel FPGA Quartus toolchain ?

I tried with cvfpu and did not work for me. Maybe I missed something, but I had the impression that you are using some SystemVerilog features not supported by Quartus Prime (v. 21.1).