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  FPGA JTAG-cable and debugger sw
Posted by: Akim - 03-28-2019, 11:45 AM - Forum: PULP General questions - Replies (5)

Hello,

We have bought couple of Genesys2 FPGA boards. We are going to use the Pulpissimo for that.

We would like to flash the test software to it and also if possible use some debugging software via JTAG.
Do you have any suggestion to use as JTAG-cable or debugging software, that you are going to support? 
Do I need to use Genesys2 PMOD connectors to connect JTAG-cable or do you have any solid solutions for that?

If understood correctly debugging software is going to need OpenOCD support and that is coming Q2/2019 for Pulpissimo. Right? 

Br,
Akim

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  OpenMP example for PULP not working
Posted by: Athena - 03-25-2019, 12:05 PM - Forum: PULP General questions - Replies (7)

Hello, 

I tried to run the openMP example given in pulp-rt-examples repository. But the simulation gets stuck at the rt_cluster_call(..); function in the test.c file. 

I have tried running Hello and Coremark examples for the same platform and they work perfectly. 

In order to find out that it gets at stuck at the rt_cluster_call, I put print statements before and after the function call. The modified "test.c" code is attached below. And the output seen is also attached .



Attached Files Thumbnail(s)
           
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  Post-synthesis simulation for pulp
Posted by: Athena - 03-07-2019, 02:37 PM - Forum: PULP General questions - Replies (1)

Hello, 

I have synthesised a particular IP of the pulp system for  ASIC using a certain compiler. Now I want to re-insert the synthesised netlist into the system and perform a post-synthesis simulation for verification. How do I go about with this?

From what I understand, when a certain simulation for say hello example (given under pulp-rt-examples) is run, all the IPS are being fetched directly from the git-hub repository instead from the locally cloned repository IP folder. Is my understanding correct?

How do I add my own changes to the exisiting IP and still run an example simulation ?


Thanks!


Regards,
Athena

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  PULP-SDK build not working
Posted by: MikkeN - 02-21-2019, 11:24 AM - Forum: PULP General questions - Replies (1)

Hi,

is there a bug in latest PULP-SDK make script?

When I am entering: make -all    
it gives an error after running a while

sdk:pulp-rt:build (pulpissimo@config_file=chips/pulpissimo/pulpissimo.json): make build install
make[1]: Entering directory `/home/mijuna/pulp-sdk/runtime/pulp-rt'
plpflags gen  --output-dir=/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo --makefile=/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/config.mk  --property=fc/archi  --property=pe/archi  --property=pulp_chip  --property=pulp_chip_family  --property=soc/cluster  --property=host/archi  --property=fc_itc  --property=udma/hyper  --property=udma  --property=udma/cpi  --property=udma/i2c/version  --property=soc/fll  --property=udma/i2s/version  --property=udma/uart  --property=event_unit/version  --property=perf_counters  --property=fll/version  --property=soc/spi_master  --property=soc/apb_uart  --property=padframe/version  --property=udma/spim  --property=udma/spim/version  --property=gpio/version  --property=rtc  --property=udma/archi  --property=soc_eu/version  --property=compiler  --property=rtc/version  --lib=rt  --lib=omp  --lib=rtio  --lib=bench
plpconf --input=pulpissimo@config_file=chips/pulpissimo/pulpissimo.json  --config=platform=rtl  --config=**/rt/type=pulp-rt --output=/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/config.json
/home/mijuna/riscv-gnu-toolchain/bin/riscv32-unknown-elf-gcc  -march=rv32imfcxpulpv2 -mfdiv -D__riscv__ -D__RT_USE_IO=1 -Os -g -fno-jump-tables -Werror -fno-tree-loop-distribute-patterns  -Wextra -Wall -Wno-unused-parameter -Wno-unused-variable -Wno-unused-function -Wundef -fdata-sections -ffunction-sections -I/home/mijuna/pulp-sdk/pkg/sdk/dev/install/include/io -I/home/mijuna/pulp-sdk/pkg/sdk/dev/install/include -include /home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/fc_config.h    -MMD -MP -c kernel/init.c -o /home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/rt/fc/kernel/init.o
cc1: error: -march=rv32imfcxpulpv2: unsupported ISA substring 'xpulpv2'
make[1]: *** [/home/mijuna/pulp-sdk/build/sdk/pulp-rt/pulpissimo/rt/fc/kernel/init.o] Error 1
make[1]: Leaving directory `/home/mijuna/pulp-sdk/runtime/pulp-rt'
Reached EOF with exit status 2
FATAL ERROR: the command 'build' has failed
make: *** [all] Error 255

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  Synthesis 8 core pulp for ASIC
Posted by: Athena - 02-11-2019, 04:41 PM - Forum: PULP General questions - Replies (3)

Hello !

I want to synthesis the pulp SoC for 65 nm ASIC technology. Given that I have the Synopsys Compiler available is there a guide as to how proper synthesis of the pulp (with 8 RI5CY) cores can be carried out on the such that the hierarchy of the system is properly maintained during optimizations. 

Is there some example script available to direct the Synopsys compiler (or some other compiler) to perform proper synthesis. 
The final goal is to be able to perform power measurements on the synthesised design. Also, is this power analysis possible with the given repository of the pulp project on github?

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  Error in build of Pulpissimo RTL platform
Posted by: idoraz - 02-09-2019, 01:17 PM - Forum: PULP General questions - Replies (1)

Hello,

We installed the SDK and the toolchain on our Linux server and have QuestaSim-64 v10.0c
 installed.
When trying to generate the PULPissimo RTL platform I am getting the following error message during the build 'phase':

** Error: ../ips/common_cells/src/stream_mux.sv(18): near "localparam": syntax error, unexpected localparam
** Error: ../ips/common_cells/src/stream_demux.sv(20): near "localparam": syntax error, unexpected localparam
** Error: ../ips/common_cells/src/popcount.sv(21): near "localparam": syntax error, unexpected localparam
make[2]: *** [modelsim_libs/common_cells_lib/common_cells_all.vmake] Error 2
make[1]: *** [build] Error 2
make: *** [build] Error 2

Do you have any clue what can be the reason for this error?

Thanks,
Ido

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  Benchmarking using Coremark
Posted by: Athena - 02-05-2019, 02:06 PM - Forum: PULP General questions - No Replies

On the github platform for PULP, under pulp-rt-examples repository the coremark benchmark has been given. 

This benchmark runs for platforms like the single-core platform PULPissimo as well as the PULP (8 core platform). 

However, in both cases I have inferred that the platforms are running at a frequency of 100 MHz. 

For instance this is the output obtained for the Pulpissimo with zero riscy core:

[TB]          30495473188 - Triggering fetch enable
# [TRACER] Output filename is: trace_core_1f_0.log
# [dbg_if_soc] WRITE32 burst @1a104008 for           4 bytes.
# [TB]          30509373188 - Waiting for end of computation
# [STDOUT-CL31_PE0] 2K performance run parameters for coremark.
# [STDOUT-CL31_PE0] CoreMark Size    : 666
# [STDOUT-CL31_PE0] Total ticks      : 535261
# [STDOUT-CL31_PE0] Total time (usecs): 5352
# [STDOUT-CL31_PE0] Iterations/Sec   : 186
# [STDOUT-CL31_PE0] ERROR! Must execute for at least 10 secs for a valid result!
# [STDOUT-CL31_PE0] Iterations       : 1
# [STDOUT-CL31_PE0] Compiler version : na
# [STDOUT-CL31_PE0] Compiler flags   : na
# [STDOUT-CL31_PE0] Memory location  : STATIC
# [STDOUT-CL31_PE0] seedcrc          : 0xe9f5
# [STDOUT-CL31_PE0] [0]crclist       : 0xe714
# [STDOUT-CL31_PE0] [0]crcmatrix     : 0x1fd7
# [STDOUT-CL31_PE0] [0]crcstate      : 0x8e3a
# [STDOUT-CL31_PE0] [0]crcfinal      : 0xe714
# [STDOUT-CL31_PE0] Correct operation validated. See README.md for run and reporting rules.
# [STDOUT-CL31_PE0] CoreMark 1.0 : 186 / na na / STATIC
# [TB]          45796773188 - Received status core: 0x00000000
# ** Note: $stop    : /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv(679)
#    Time: 45796773188 ps  Iteration: 0  Instance: /tb_pulp
# Break at /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv line 679
# Stopped at /home/ashwini/pulp-sdk/pulpissimo-master/sim/../rtl/tb/tb_pulp.sv line 679
# End time: 14:51:20 on Feb 05,2019, Elapsed time: 0:05:38
# Errors: 0, Warnings: 15


From the total time taken and the total ticks fields, it can be deduced that the platform is running at a speed of 100 MHz. 

How was this frequency chosen?

Also, is there a way to change this frequency from the coremark.patch file (or any other file for that matter) that has been given with the coremark folder under pulp-rt-examples. 

Another interesting result of running the coremark example was that I obatined the same performance numbers (as listed above) for PULP and PULPissimo (with RISCY core). Does this mean that when coremark is running on PULP it is just giving the performance number of the core and the not the entire architecture? or How to interpret these values after running the coremark. Is it only evaluating the performance of a single core regardless of the platform?

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  Error Linux Cross Compiler
Posted by: Athena - 01-28-2019, 09:57 PM - Forum: PULP General questions - Replies (3)

Hello!


While following the instructions to install the RISC-V GNU compiler as listed here :https://github.com/pulp-platform/pulp-riscv-gnu-toolchain.

I installation for the linux cross compiler is failing.
On running this command on the terminal: 

Code:
./configure --prefix=/opt/riscv --with-arch=rv32g --with-abi=ilp32d
make linux


I get the error message saying:
 /include/atomic.h:826:3: error: #error ATOMIC_EXCHANGE_USES_CAS has to be defined.

I have attached a screenshot showing the error with this post. 

Is there any fix for this? or Am I doing something wrong?

I am running this on Ubuntu 18.04 and I have set the gcc version to 5. Also, the Newlib compilation is performed successfully.

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  Estimating Energy and Power Consumption in PULP
Posted by: Adi - 01-24-2019, 08:29 AM - Forum: PULP General questions - Replies (1)

Hi,

If I want to estimate the energy and power consumption of a specific software which is run on PULP (let's say PULPino, PULPissimo or bigPULP) with an HWPE that I added, what is the proper way of doing it?
In addition, is there a way of estimating the area?

Thanks!
Adi

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  RISCY modifications possibilties
Posted by: Athena - 01-23-2019, 11:00 AM - Forum: PULP General questions - Replies (4)

Riscy and zero riscy cores based on the RISC V ISA are available as a part of different PULP systems. The specific custom extensions in the RISC V ISA are supported by the compiler. 

I was wondering If I can make changes to the RISCY core for eg adding a new h/w block like the h/w loop controller.
First of all with the given SDK is that even possible?
And is there a possibility of getting software support for such modifications. 

Thanks!

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