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  Simple RISC-V Assembly Instructions Verification
Posted by: ufsahu - 08-19-2020, 07:48 AM - Forum: PULP General questions - Replies (2)


I am new to RISC-V and PULPissimo. So far, using the following Makefile, I have been able to generate C based test cases for verifying general C commands:

PULP_APP = test

include $(PULP_SDK_HOME)/install/rules/pulp_rt.mk

When I am trying to add basic asm code as inline assembly in the C test, it provides error on those specific commands.

I added the following code in the test.c file:

asm( "mov r0, r0\n\t" 
     "mov r0, r0\n\t" 
     "mov r0, r0\n\t" 
     "mov r0, r0" );

I received the following errors:

test.c: Assembler messages:
test.c:15: Error: unrecognized opcode mov r0,r0'
test.c:16: Error: unrecognized opcodemov r0,r0'
test.c:17: Error: unrecognized opcode mov r0,r0'
test.c:18: Error: unrecognized opcodemov r0,r0'

Is there a simple way of adding inline assembly in C test cases, and verifying for example load and store instructions, or more instruction types? The compiler is able to run test.c file using the above Makefile method and I was hoping to keep that constant and work it around the inline assembly in a simple way.

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  Error while running helloworld in PULPino
Posted by: Tresa Febina Francis - 08-12-2020, 05:06 PM - Forum: PULP General questions - No Replies

root@tresa-Inspiron-5567:~/pulpino/sw/build1# make helloworld
[  0%] Built target bench
[  0%] Building C object CMakeFiles/crt0.dir/ref/crt0.riscv.S.o
/root/pulpino/sw/ref/crt0.riscv.S:17:3: error: expected identifier or '(' before '.' token
   .section .text
/root/pulpino/sw/ref/crt0.riscv.S:84:3: error: unknown type name 'addi'
   addi x10, x0, 0
/root/pulpino/sw/ref/crt0.riscv.S:84:17: error: expected identifier or '(' before numeric constant
   addi x10, x0, 0
/root/pulpino/sw/ref/crt0.riscv.S:89:3: error: unknown type name 'mv'
   mv a0, s0
/root/pulpino/sw/ref/crt0.riscv.S:91:3: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'jal'
   jal  x1, exit
/root/pulpino/sw/ref/crt0.riscv.S:254:5: error: invalid preprocessing directive #These
   # These don't have to do anything since we use init_array/fini_array.
/root/pulpino/sw/ref/crt0.riscv.S:254:14: warning: missing terminating ' character
   # These don't have to do anything since we use init_array/fini_array.
/root/pulpino/sw/ref/crt0.riscv.S:265:3: error: expected identifier or '(' before '.' token
   .org 0x00
CMakeFiles/crt0.dir/build.make:81: recipe for target 'CMakeFiles/crt0.dir/ref/crt0.riscv.S.o' failed
make[3]: *** [CMakeFiles/crt0.dir/ref/crt0.riscv.S.o] Error 1
CMakeFiles/Makefile2:3980: recipe for target 'CMakeFiles/crt0.dir/all' failed
make[2]: *** [CMakeFiles/crt0.dir/all] Error 2
CMakeFiles/Makefile2:5086: recipe for target 'apps/helloworld/CMakeFiles/helloworld.dir/rule' failed
make[1]: *** [apps/helloworld/CMakeFiles/helloworld.dir/rule] Error 2
Makefile:720: recipe for target 'helloworld' failed
make: *** [helloworld] Error 2

Got this error while running helloworld.
Kindly look into this error and help me out.
Thanks in advance!

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  Which FPGA?
Posted by: thalyson - 08-10-2020, 07:35 PM - Forum: PULP General questions - Replies (1)

Hello everyone

The Pulpissimo page on GitHub says:

"At the moment the following boards are supported:

  Digilent Genesys2
  Xilinx ZCU104
  Xilinx ZCU102
  Digilent Nexys Video

The question is: which one is better to start working with Pulpissimo? Is there any difference between them? Is there a "easier" board?


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  Cannot open linker script file riscv.ld
Posted by: nayan - 08-05-2020, 11:04 AM - Forum: PULP General questions - Replies (1)

I downloaded pulp-riscv-gnu-toolchain and did installation(PULP). When i try to compile a program using riscv32-unknown-elf-gcc, I get the following error

/opt/riscv/lib/gcc/riscv32-unknown-elf/7.1.1/../../../../riscv32-unknown-elf/bin/ld: cannot open linker script file riscv.ld: No such file or directory

collect2: error: ld returned 1 exit status

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  Modifications of the HERO platform
Posted by: Olivier - 07-06-2020, 07:40 AM - Forum: PULP General questions - Replies (2)


I'm very interested by the HERO platform on the ZC706 FPGA board. I tried to modify bigpulp by defining 2 clusters of 3 cores each. To do this, I changed the number of clusters and cores in the bigpulp/fe/rtl/includes/pulp_soc_defines.sv file and the hero_sdk/pulp_sdk/pulp_configs/configs/systems/hero-z-7045.json file.

To generate the bitstream, I followed the steps described in this link https://github.com/pulp-platform/bigpulp. And to generate the SDK, I followed the steps described in this link https://pulp-platform.org/hero/doc/software/.

However, I was not able to run the "hero-openmp-examples" programs. In the case of the mm-large program, matrix multiplication is correctly executed on ARM, but for the part to be executed on bigPulp it is frozen.

Did I modify the right files for the bigPULP part and the HERO-SDK part?
Otherwise do you have any idea what the problem is?

Thanks in advance.

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  32bit data memory write & read
Posted by: RiscV - 07-03-2020, 09:53 AM - Forum: PULP General questions - No Replies

I am trying to transmit a 32 bit data from memory to UART through Udma. The problem I am facing is udma transmit bus carry only 1byte data. The code I had written to load 32 bit data to memory is:

//loading data to memory
lui x16,0x12345
addi x16,x16,0x678   // 32 bit value- 12345678
lui x14, 0x1c010     // address location 1c01000
sw x16,x14
In the udma_tx_ bus the data found is 78787878 in the address location 1c01000.
I checked the memory banks separately. 78 is copying in all four banks, memory write is not happening at that time.What should I do to transmit the entire 32 bit data to 1c01000 location. I want 12345678 data in 1c01000. Please help me.

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  udma memory to memory data transfer test bench
Posted by: RiscV - 06-29-2020, 09:52 AM - Forum: PULP General questions - Replies (2)

Currently I am writing a test bench for transferring a 32 bit data from one location to another memory location in RISCV  pulp. I am bit confused how to set the address of DMA transmit bus and the procedure for transferring the data. Can you help me regarding this

code I wrote for transferring data without DMA is

li x15,64
LUI x14, 0x1c000 // Source address selected is 0x1c000001
sw x15, 001(x14)
LUI x13, 0x1c010  // destination address is 0x1c01000
sw x14, 0(x13)

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  Questions regarding Runtime/SDK
Posted by: heavySea - 06-22-2020, 01:54 PM - Forum: PULP General questions - Replies (2)


I'm currently starting a project based on Pulpissimo with an Ibex core as Fabric Controller. I got everything set up as described in the Readme. The RTL simulation works fine and I got a (working) implementation running on a Nexys A7 board (ported from the Nexys Video implementation) which I want to use to test some peripherals.
I connect to the board by using a Digilent HS2 JTAG debugger with OpenOCD from the pulp-SDK.

At this point I have a few questions (and problems) regarding the runtime/PulpOS.

There are currently three repositories providing SW support for Pulp/Pulpissimo. The pulp-builder, pulp-sdk, and the pulp-runtime.

I understand that the pulp-runtime is currently a simplified version of the runtime. But as i noticed it seems to have different way of configuring/building.
A) As it is a newer runtime, do you plan to extend this further to replace the "old sdk" at some point?
B) Currently the pulp-runtime supports only the riscy core. Would it be possible to support the ibex as well?

The simple runtime worked on the FPGA out of the box with the riscy core. That was nice Smile 

In the readme of the pulpissimo the pulp-builder is the suggested package to use the runtime and therefor is the same as an SDK, right? But what is the pulp-SDK then?
The runtime and api files seems to be similar. But I encountered different problems with both when using the examples.

E.g. the hello uart example:
With the pulp-builder SDK the Code doesn't even reach the main() part but hangs somewhere during the boot/configuration part.
With the pulp-sdk i can use the UART with printf but not using the UART driver. Also only after using this fix.

C) Now I'm not quite sure which one to use. For which should I use my time to investigate my problems?

Also the SDK seems to use deprecated drivers for the examples (at least the name of the folder is like that). So..
D) Is there any documentation of the runtime and its APIs except for the auto generated docs and the examples in the SDK?
The pulp-builder has an empty Doc folder.

E) Regarding a comment on this issue the support of the SDK regarding the ibex core is not really complete. It seems like nothing has changed much since then.
Are you planing to keep the support for the ibex core?

I hope someone finds the time to answer my questions and I'm looking forward to work with the pulp platform. Smile

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  Data relocation when using LOAD_L2=STANDALONE
Posted by: LPLA - 06-09-2020, 02:10 PM - Forum: PULP General questions - Replies (4)


as you know PULPissimo has an option to boot from flash by setting the LOAD_L2 parameter in the tb_pulp.sv to STANDALONE.
As far as I know it won't actually boot from flash but instead load the data from flash to the L2 and execute it. Is this still the case?

So I was running the hello example from the pulp_rt_examples using the STANDALONE variant.
This works just fine but I was wondering about the contents of the different memories after the end of the computation.

We can see that when using STANDALONE the flash memory uses its preload feature to contain "slm_files/flash_stim.slm" which should be the image of the hello example.
When instead using JTAG there is a different image loaded into L2 called stim.txt.

There are several question which I hope someone can answer:

Is there a reason why the actual data from those images is different?
I'm not talking about formatting but rather the actual data itself.
For example:

The first few lines of the .slm file:
@00000000 00
@00000001 70
@00000002 00
@00000003 00
@00000004 04
@00000005 00
@00000006 00
@00000007 00
@00000008 80
@00000009 80
@0000000A 00
@0000000B 1C

The first few lines of the .txt file:

I'm pretty sure that the memory called "boot rom" contains the boot code which is unrelated to the executed (hello example) code. Is this correct?
The code of the hello example should reside somewhere in L2. Now using QuestaSim to check the contents of the different L2 sections I get confused.
There is some data in .../bank_sram_pri0_i/MEM which looks a bit scattered as there are some undefined entries.
The data in .../bank_sram_pri1_i/MEM is more coherent.
Also there is a bit of data in every 0 cut of every CUT X.
By that i mean ...CUTS[X]/RTL_0/bank_i/cut_0/MEM.

What actually resides in pri0, pri1, cut_0?
I found the data of the stim.txt in L2 (in pri0 but not starting at 0x00000000) but not in a coherent way.
Why is this the case even tho I am using STANDALONE instead of JTAG.

In regards to my previous question there is also the boot-code repo which is what I am currently trying to extend.
If I'm not mistaken the boot_code.cde which I linked to in the above post is the binary of the boot_code.c found in this repo, is that correct?
Looking at the linker script link.ld we can see that there are only two entries in the memory table: ROM and L2.
How is data actually relocated from flash to L2? As far as I remember the flash is not memory mapped or is it?
I'm trying to modify the files in a way which allows me to load (preloaded) data from flash to defined addresses in L2, similar to how the (preloaded) hello example has to somehow be relocated.
Unfortunately I'm not allowed to modify boot_code.c so I'm guessing I have to modify the linker script link.ld and the main startup file crt0.S or add additional files.
Does anyone know if it is actually possible to load data from an arbitrary address in flash to an arbitrary address in L2 during boot phase?

Thank you,

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  Some questions about the HERO platform
Posted by: Olivier - 06-04-2020, 03:38 PM - Forum: PULP General questions - Replies (3)


I'm new to using the PULP environment and currently I am trying to familiarize myself with the HERO platform implemented on my ZC706 board and I have a few questions:

• I saw that with OpenMP the workload to execute is sent to the cluster with 8 RISC-V cores.
However, can I choose precisely which cores will be used to run a workload ?
For example, I would like the workload W1 to be executed by cores PE0, PE1 and PE2 and the workload W2 to be executed by cores PE M to PE N-1.

• I suppose it is possible with the ZC706 FPGA board to have 2 clusters of 4 RISC-V cores.
Similar to the previous question, can I choose which cluster will run a workload ?

• I saw in the file "fe/rtl/includes/pulp_soc_defines.sv" on Github that it is possible to define an FPU. But I can't find the apu_package.sv file mentioned in the comment on line 45 to add an FPU.
Is it possible to add an FPU in big-pulp?
Is the FPU shared between the cores or is it one FPU per core ?

• Last question, Is it possible to add a HWCE to a cluster ?

Thanks in advance

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