Cheshire with two cores

[andlo47]

Hi all,

I'm trying to generate a bit file for Cheshire v0.1.0 with two cores for the Genesys2 board using Vivado 2023.2, but get an error stating that timing constraints are not met.
I can generate the bit file from an earlier commit, f316617, of the Cheshire repo. I did remove the USB support as it would not fit on the FPGA of Genesys2.

I'm quite new to this and would appreciate any help. I'm not sure where to start looking.

Regards,
/Andreas

[kgf]

I am guessing that some of the additions proved a bit too much for the timing constraints. You could (in most cases) relax the constraints to get through it. Note that for most PULP IP, the code is not FPGA optimized, we use FPGAs for emulation and not as the primary target. That is why, the speed at which it works is not much of an issue. Our usual targets are ASIC designs where the optimizations may differ quite a bit from FPGAs (due to internal resources like BRAMs, DSPs etc).

Of course it is not like the timing contraints should go from 50ns to 5000ns.. that could point out to an issue somewhere

[antp]

Hi, Were you able to boot linux on Cheshire dual core?
I've been trying but without success.
I made the changes mentioned in this issue.
https://github.com/pulp-platform/cheshire/issues/175

Any helps, references, pointers would be extremely appreciated.
Thanks

[kgf]

Can you let us know where you are stuck, the original question had issues during synthesis. Is this the case for you as well. At what stage are you stuck, which branch are you using, which FPGA you are using?

AFAIK this is something that is working in our environment and is in active use.

[antp]

Hello, Thank you so much for stepping in. I am using the main branch of cheshire. Cloned and built using the process provided here.
https://pulp-platform.github.io/cheshire/tg/xilinx

I have a VCU118 board instead of VCU128 so I used the changes mentioned in this repo https://github.com/mrbilandi/cheshire/tree/VCU118 (which I believe has pull request into main branch of cheshire). I am using STARTUPE3 and Xilinx QSPI IP to boot linux from FPGA flash (since vcu118 has no SD card support and PMOD has signal integrity issues).

My single core version works perfect and linux boots successfully but when I changed NumCores to 2 and built, (linux image remained the same), I see no output on UART terminal. Not even the ZSL loads that prints cat logo and some system information. I used OpenOCD to debug and was able to run baremetal helloworld.spm.elf on each core individually (by changing util/openocd.common.tcl `coreid` parameter to 0 and 1 respectively for each core.

I am not sure if I need to change any other parameters aside from NumCores to be able to run linux on dual core system.
The issue: https://github.com/pulp-platform/cheshire/issues/175 describes my situation best.
Any guidance is extremely appreciated. Thanks in advance