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Cheshire with two cores
Forum: PULP General questions
Last Post: tomkathy
06-18-2025, 09:17 AM
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【新手必讀】Relx電子菸煙彈選購指南與保養技巧
Forum: PULP General questions
Last Post: mmrnkbqfexgs
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Understanding HWPE integr...
Forum: PULP General questions
Last Post: sillycorn
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missing package in pulp-s...
Forum: PULP General questions
Last Post: Renryant
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Role of gapy, list of per...
Forum: PULP General questions
Last Post: yoss
04-25-2025, 01:41 PM
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Pulp - make build
Forum: PULP General questions
Last Post: tomkathy
04-09-2025, 07:58 AM
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Unable to compile and run...
Forum: PULP General questions
Last Post: victorgervasio
03-25-2025, 09:30 AM
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__builtin_pulp
Forum: PULP General questions
Last Post: yoss
02-18-2025, 04:31 PM
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XpulpNN march
Forum: PULP General questions
Last Post: yoss
02-06-2025, 12:47 PM
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Help with llvm/clang comp...
Forum: PULP General questions
Last Post: ThomasMuyal
01-23-2025, 10:10 PM
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Opentitan on FPGA |
Posted by: gtelzur - 06-05-2022, 07:51 AM - Forum: PULP General questions
- Replies (2)
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I am interested in implementing Opentitan on a cheap FPGA. The reference board, CW310, is very expensive.
Can cheap FPGAs such as Tang nano 9k, ICE40, ECP5, etc' be used? My preference is to use open-source tools as much as possible. Perhaps these FPGAs don't have enough resources for the whole Opentitan and only a partial implementation is possible!?
I would appreciate any comments/recommendations.
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Compile and Create a testbench for cva6 tlb |
Posted by: Typhoon - 06-01-2022, 05:06 PM - Forum: PULP General questions
- Replies (1)
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Hi all,
I am new to the cva6, and I have a project to extend the functionality of the cva6 tlb.
In order to do so, I plan to create a testbench and compile the tlb module
to validate the current and extended functionalities. However, I am stuck at the
compilation step to compile only the tlb module and its related modules/files.
I would be appreciated if someone would suggest a starting point to accomplish such task?
Best,
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Error at GPIO input interrupt example |
Posted by: ivanhira - 05-04-2022, 03:36 PM - Forum: PULP General questions
- No Replies
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Hi,
I'm trying to simulate Pulpissimo using the test examples from pulp-rt-examples. I'm using the releases v7.0.0 of Pulpissimo, with some modifications at pad_control.sv fixing the mux indexes for the last six PADs. I've tried with the GPIO input, all PADs works. The problem was in the GPIO input interrupt example, the code works fine testing one GPIO pin at a time, but I wanted to test multiple pins by setting events with the same function handler in all pins. Doing that, the first and second PADs works fine, but it fails at the third PAD.
Here is the transcript in Questasim:
PHP Code: <?php
run 13ms
# [CORE] Core settings: PULP_SECURE = 1, N_PMP_ENTRIES = 16, N_PMP_CFG 4
# [TB] 0ns - Entry point is set to 0x1c008080
# [TB] 0ns - Asserting hard reset
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "fs/file_0_0.txt" for writing.
# No such file or directory. (errno = ENOENT) : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_fs_handler.sv(269)
# Time: 0 ps Iteration: 0 Instance: /tb_pulp/i_fs_handler/FS_PRINTF_CLUSTER
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "fs/file_31_0.txt" for writing.
# No such file or directory. (errno = ENOENT) : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_fs_handler.sv(269)
# Time: 0 ps Iteration: 0 Instance: /tb_pulp/i_fs_handler/FS_PRINTF_FC
# [TB] 1ns - Using FLL
# [TB] 1ns - Not using CAM SDVT
# Loading default stimuli
# [JTAG] SoftReset Done( 701ns)
# [JTAG] Bypass Test Passed ( 33301ns)
# [JTAG] Tap ID: 249511c3 ( 43701ns)
# [JTAG] Tap ID Test PASSED ( 43701ns)
# [test_mode_if] 50301ns - Init
# [TB] 50301ns - Enabling clock out via jtag
# [test_mode_if] 51801ns - Setting confreg to value 002.
# [TB] 51801ns - jtag_conf_reg set to 002
# [TB] 51801ns - Releasing hard reset
# [TB] 53401ns - Init PULP TAP
# [pulp_tap_if] WRITE32 burst @1c008080 for 4 bytes.
# [TB] 67501ns - Write32 PULP TAP
# [JTAG] R/W test of L2 succeeded
# [TB] 177701ns - Halting the Core
# [TB] 236501ns - Writing the boot address into dpc
# [TB] 280601ns - Loading L2 via JTAG
# [JTAG] Loading L2 with pulp tap jtag interface
# [pulp_tap_if] WRITE32 burst @1c000000 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c000400 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c000800 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c000c00 for 840 bytes.
# [pulp_tap_if] WRITE32 burst @1c008000 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c008400 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c008800 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c008c00 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c009000 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c009400 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c009800 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c009c00 for 1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c00a000 for 832 bytes.
# [pulp_tap_if] WRITE32 burst @1c010000 for 240 bytes.
# [TB] 10977201ns - Resuming the CORE
# [TB] 11550701ns retrying debug reg access
# [TB] 11580001ns retrying debug reg access
# [TB] 11609301ns retrying debug reg access
# [TB] 11638601ns retrying debug reg access
# [TB] 11667901ns retrying debug reg access
# [TB] 11697201ns retrying debug reg access
# [TB] 11726501ns retrying debug reg access
# [TB] 11755801ns retrying debug reg access
# [TB] 11799801ns - Waiting for end of computation
force -freeze pad_spim_sdio0 1 0, 0 20us
run 1ms
# [STDOUT-CL31_PE0] Got edge.
force -freeze pad_spim_sdio1 1 0, 0 20us
run 1ms
# [STDOUT-CL31_PE0] Got edge.
force -freeze pad_spim_sdio2 1 0, 0 20us
run 1ms
# 15001366ns: Illegal instruction (core 0) at PC 0x00000000:
# [STDOUT-CL31_PE0] [ [35mRT(31,0) [0m] [33mWARNING [0m: Reached illegal instruction (PC: 0x0, opcode: 0x0
# [TB] 15302201ns - Received status core: 0x7fffffff
# ** Note: $stop : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_pulp.sv(857)
# Time: 15302201 ns Iteration: 0 Instance: /tb_pulp
# Break at /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_pulp.sv line 857
And here is the c code of the test:
Code: /*
* This example shows how to block the core until a GPIO
* value has changed.
*/
#include <stdio.h>
#include <rt/rt_api.h>
#include <stdint.h>
#if PULP_CHIP == CHIP_GAP
#define GPIO 0
#else
#define GPIO 13
#endif
#define NB_EDGE 10
static int edges = 0;
static void gpio_handler(void *arg)
{
printf("Got edge.\n");
edges++;
}
// Testing one GPIO PAD
/*
int main()
{
if (rt_event_alloc(NULL, 1)) return -1;
// GPIO initialization
rt_gpio_init(0, GPIO);
rt_pad_set_function(GPIO, 1); //pad_func=1 means gpio functionality. pad_func=0 is default
// Configure GPIO as an inpout
rt_gpio_set_dir(0, 1<<GPIO, RT_GPIO_IS_IN);
// Trigger notifications on both rising and falling edges
rt_gpio_set_sensitivity(0, GPIO, RT_GPIO_SENSITIVITY_EDGE);
// Set the event for the GPIO.
// Note that we use an IRQ event instead of a normal one so that
// the callback is called directly from the IRQ handler.
rt_gpio_set_event(0, GPIO, rt_event_irq_get(gpio_handler, (void *)GPIO));
// Now wait for a few edges and see how long it takes
unsigned long long start = rt_time_get_us();
while(edges < NB_EDGE)
{
rt_event_yield(NULL);
}
unsigned long long end = rt_time_get_us();
printf("Got %d edges in %d us\n", NB_EDGE, end - start);
return 0;
}*/
// Testing all GPIO PADs
int main()
{
if (rt_event_alloc(NULL, 1)) return -1;
// GPIO initialization
for (int i=0; i<32; i++)
{
rt_gpio_init(0, i);
rt_pad_set_function(i, 1); //pad_func=1 means gpio functionality. pad_func=0 is default
}
// Configure GPIO as an inpout
rt_gpio_set_dir(0, 0xffffffff, RT_GPIO_IS_IN);
// Trigger notifications on both rising and falling edges
for (int i=0; i<32; i++)
{
rt_gpio_set_sensitivity(0, i, RT_GPIO_SENSITIVITY_RISE);
}
// Set the event for the GPIO.
// Note that we use an IRQ event instead of a normal one so that
// the callback is called directly from the IRQ handler.
for (int i=0; i<32; i++)
{
rt_gpio_set_event(0, i, rt_event_irq_get(gpio_handler, (void *)i));
while(edges == 0)
{
rt_event_yield(NULL);
}
rt_gpio_set_event(0, i, NULL);
edges = 0;
}
return 0;
}
The only thing I did before "run 13ms" is forcing all PADs to 0. And I verified that the problem is not in the pad_spim_sdio2, I tried starting with GPIO 2 then it failed at GPIO 4.
Thanks in advance.
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FLL IPs |
Posted by: vpandey6 - 02-28-2022, 02:18 PM - Forum: PULP General questions
- Replies (2)
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Hi all,
I guess the current FLL model in PULP setup is not synthesizable. I want to make my own ASIC and looking for open source FLL IPs.
Has anyone used such an IP?
Also wanted to check on my understanding that FLL in its current form is not synthesizable.
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Docker Container for PULP-based systems |
Posted by: beeblebrox - 02-09-2022, 08:05 AM - Forum: PULP General questions
- No Replies
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A docker container for the RISC-V GNU compiler toolchain has been contributed to this forum. There exists already a Docker container with all the Snitch tools (source and container). A Docker container lowers the entry hurdle, streamlines development on different host environments and allows for CI of projects using PULP infrastructure.
We could merge the efforts into a single Docker container including (but not limited to):
- GCC and LLVM toolchains for both PULP and Snitch systems
- Simulators such as GVSOC (PULP) and banshee (Snitch)
- Verilated models of PULP systems (such as the Snitch-cluster) for cycle-accurate simulations
Please add suggestions for components that should be added to this unified container.
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Docker image for the RISC-V GNU compiler toolchain |
Posted by: Coderitter GmbH - 02-08-2022, 12:55 PM - Forum: PULP General questions
- Replies (3)
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Hello everyone,
to ease the use of the compiler, at least in our company, we created a Docker image of the latest version 7.1.1. that we want to share with the community.
https://hub.docker.com/repository/docker...in/general
You can use it like this:
In your project, create a shell script for the RISC V compiler executable. You can name the file "riscv32-unknown-elf-gcc" which is the exact name of the RISC V compiler executable inside the Docker container. Put the following content inside of it.
Code: #!/bin/sh
docker run --rm --entrypoint riscv32-unknown-elf-gcc --volume $PWD:/hostdir coderitter/pulp-riscv-gnu-toolchain "$@"
This call to "docker run" will create a temporary Docker container with the current directory mounted into Docker container. It then executes the RISC V compiler executable and forwards any parameters which were made when the script was executed.
The last step is to set the permission of the file so that is executable.
Code: chmod a+x riscv32-unknown-elf-gcc
Now you can use the script as if the compiler itself was installed in your host system.
Code: ./riscv32-unknown-elf-gcc -std=c99 -march=rv32imfdcxpulpv2 src -o build/firmware
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Pulpino UART |
Posted by: nemanja-rv - 02-04-2022, 05:02 PM - Forum: PULP General questions
- No Replies
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Hi,
I spent some time in the previous few days to port Pulpino platform to ZC706 board and Vivado 2019.2.
I successfully brought up the board and as far as I could see, the spiloader can download the compiled code to the ri5cy core. The core boots and starts working.
One minor thing that I cannot seem to solve is the UART baudrate. I have tried setting the microcom running on linux to 115200 baudrate but it just receives some wrong characters. The app that I am running on the Pulpino is fpga_test app so it should continously transmit something over the uart. How is the baudrate set for Uart? In addition, I noticed that the spiloader app sets the clock frequency (configuration of the clk_wiz) to 5MHz. I would like to change that parameter, to set to 50MHz or any other but I assume there has to be some other change in sw code. I assume this also have impact on baud rate configuration.
Any advice would be appreciated.
Thanks,
NK
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