Hi, 

I'm trying to simulate Pulpissimo using the test examples from pulp-rt-examples. I'm using the releases v7.0.0 of Pulpissimo, with some modifications at pad_control.sv fixing the mux indexes for the last six PADs. I've tried with the GPIO input, all PADs works. The problem was in the GPIO input interrupt example, the code works fine testing one GPIO pin at a time, but I wanted to test multiple pins by setting events with the same function handler in all pins. Doing that, the first and second PADs works fine, but it fails at the third PAD.

Here is the transcript in Questasim:

<?php 

run 13ms

# [CORE] Core settings: PULP_SECURE =           1, N_PMP_ENTRIES =          16, N_PMP_CFG           4

# [TB]       0ns - Entry point is set to 0x1c008080

# [TB]       0ns - Asserting hard reset

# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "fs/file_0_0.txt" for writing.

# No such file or directory. (errno = ENOENT)    : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_fs_handler.sv(269)

#    Time: 0 ps  Iteration: 0  Instance: /tb_pulp/i_fs_handler/FS_PRINTF_CLUSTER

# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "fs/file_31_0.txt" for writing.

# No such file or directory. (errno = ENOENT)    : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_fs_handler.sv(269)

#    Time: 0 ps  Iteration: 0  Instance: /tb_pulp/i_fs_handler/FS_PRINTF_FC

# [TB]       1ns - Using FLL

# [TB]       1ns - Not using CAM SDVT

# Loading default stimuli

# [JTAG] SoftReset Done(    701ns)

# [JTAG] Bypass Test Passed (  33301ns)

# [JTAG] Tap ID: 249511c3 (  43701ns)

# [JTAG] Tap ID Test PASSED (  43701ns)

# [test_mode_if]   50301ns - Init

# [TB]   50301ns - Enabling clock out via jtag

# [test_mode_if]   51801ns - Setting confreg to value 002.

# [TB]   51801ns - jtag_conf_reg set to 002

# [TB]   51801ns - Releasing hard reset

# [TB]   53401ns - Init PULP TAP

# [pulp_tap_if] WRITE32 burst @1c008080 for           4 bytes.

# [TB]   67501ns - Write32 PULP TAP

# [JTAG] R/W test of L2 succeeded

# [TB]  177701ns - Halting the Core

# [TB]  236501ns - Writing the boot address into dpc

# [TB]  280601ns - Loading L2 via JTAG

# [JTAG] Loading L2 with pulp tap jtag interface

# [pulp_tap_if] WRITE32 burst @1c000000 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c000400 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c000800 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c000c00 for         840 bytes.

# [pulp_tap_if] WRITE32 burst @1c008000 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c008400 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c008800 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c008c00 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c009000 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c009400 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c009800 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c009c00 for        1024 bytes.

# [pulp_tap_if] WRITE32 burst @1c00a000 for         832 bytes.

# [pulp_tap_if] WRITE32 burst @1c010000 for         240 bytes.

# [TB] 10977201ns - Resuming the CORE

# [TB] 11550701ns retrying debug reg access

# [TB] 11580001ns retrying debug reg access

# [TB] 11609301ns retrying debug reg access

# [TB] 11638601ns retrying debug reg access

# [TB] 11667901ns retrying debug reg access

# [TB] 11697201ns retrying debug reg access

# [TB] 11726501ns retrying debug reg access

# [TB] 11755801ns retrying debug reg access

# [TB] 11799801ns - Waiting for end of computation

force -freeze pad_spim_sdio0 1 0, 0 20us

run 1ms

# [STDOUT-CL31_PE0] Got edge.

force -freeze pad_spim_sdio1 1 0, 0 20us

run 1ms

# [STDOUT-CL31_PE0] Got edge.

force -freeze pad_spim_sdio2 1 0, 0 20us

run 1ms

# 15001366ns: Illegal instruction (core 0) at PC 0x00000000:

# [STDOUT-CL31_PE0] [ [35mRT(31,0) [0m]  [33mWARNING [0m: Reached illegal instruction (PC: 0x0, opcode: 0x0

# [TB] 15302201ns - Received status core: 0x7fffffff

# ** Note: $stop    : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_pulp.sv(857)

#    Time: 15302201 ns  Iteration: 0  Instance: /tb_pulp

# Break at /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_pulp.sv line 857 

Hello everyone,

    I am working on implementing of PULPino on FPGA Artix-7 100t and I can I've been able to run some small programs about GPIO and UART etc. But now i am trying to find out a way to read the memory value as well as the register files. According to the datasheet, il tells me that i could use SPI slave to do this, but there is not any more description about it. Then i turn to the testbench in the folder /tb and try to figure out the protocol of SPI Slave. For example, I try to send the 8bits cmd 0x0B, then 32bits address 0x1A110404 and finally try to receive the value in register x1, but there is noting back. I also try to read the system verilog code about the SPI slave, but i could not find somting special.
    So has anyone used SPI slave successfully? Or has there some other ways to read the specific memory value and register files?

Thanks for your help.

Philip

Is there a QEMU support for xpulpv2 extension instructions?

Hi all,
I guess the current FLL model in PULP setup is not synthesizable. I want to make my own ASIC and looking for open source FLL IPs.
Has anyone used such an IP?
Also wanted to check on my understanding that FLL in its current form is not synthesizable.

Hi,
I wonder what happened to pulp-nn-mixed repository. Is it going to be available any time soon? Thanks.

Best regards,
Beran

A docker container for the RISC-V GNU compiler toolchain has been contributed to this forum. There exists already a Docker container with all the Snitch tools (source and container). A Docker container lowers the entry hurdle, streamlines development on different host environments and allows for CI of projects using PULP infrastructure.

We could merge the efforts into a single Docker container including (but not limited to):

• GCC and LLVM toolchains for both PULP and Snitch systems
  
• Simulators such as GVSOC (PULP) and banshee (Snitch)
  
• Verilated models of PULP systems (such as the Snitch-cluster) for cycle-accurate simulations
  

Hello everyone,

to ease the use of the compiler, at least in our company, we created a Docker image of the latest version 7.1.1. that we want to share with the community.

https://hub.docker.com/repository/docker...in/general

You can use it like this:

In your project, create a shell script for the RISC V compiler executable. You can name the file "riscv32-unknown-elf-gcc" which is the exact name of the RISC V compiler executable inside the Docker container. Put the following content inside of it.

Hi,

I spent some time in the previous few days to port Pulpino platform to ZC706 board and Vivado 2019.2.
I successfully brought up the board and as far as I could see, the spiloader can download the compiled code to the ri5cy core. The core boots and starts working. 

One minor thing that I cannot seem to solve is the UART baudrate. I have tried setting the microcom running on linux to 115200 baudrate but it just receives some wrong characters. The app that I am running on the Pulpino is fpga_test app so it should continously transmit something over the uart. How is the baudrate set for Uart? In addition, I noticed that the spiloader app sets the clock frequency (configuration of the clk_wiz) to 5MHz. I would like to change that parameter, to set to 50MHz or any other but I assume there has to be some other change in sw code. I assume this also have impact on baud rate configuration. 

Any advice would be appreciated.

Thanks,
NK

Hello everyone,

i want the RISC-V GNU Compiler Toolchain to work on OS X. Here are my steps so far and what goes wrong.

Hi all,

I am planning to do some work on porting the Pulpissimo platform to several different FPGA boards. One will be Kintex KC705 and another one would Zynq ZC706. Potentially, there might also be a port to some of application specific boards, again, based on Kintex chip. 

I have run an out-of-box run for Zedboard just to get the feeling about the sizes of different iPs. One thing that I've noticed is that the clock frequency is set to 20MHz for the Zedboard and that the Vivado synthesis/implementation does report a fail in timing closure even for such a low clock frequency. 

My actual idea was to port to ZC706 and KC706 and to use a clock frequency of somewhere in the neighborhood of 80MHz-100MHz. 
Is this something that should be achievable? What would be a maximal achievable frequency for FPGA synthesis? 

In addition, have you been doing any synthesis runs for TSMC 40nm LP?

Thanks.

Cheers,
NK