Hello everyone,

to ease the use of the compiler, at least in our company, we created a Docker image of the latest version 7.1.1. that we want to share with the community.

https://hub.docker.com/repository/docker...in/general

You can use it like this:

In your project, create a shell script for the RISC V compiler executable. You can name the file "riscv32-unknown-elf-gcc" which is the exact name of the RISC V compiler executable inside the Docker container. Put the following content inside of it.

Hi,

I spent some time in the previous few days to port Pulpino platform to ZC706 board and Vivado 2019.2.
I successfully brought up the board and as far as I could see, the spiloader can download the compiled code to the ri5cy core. The core boots and starts working. 

One minor thing that I cannot seem to solve is the UART baudrate. I have tried setting the microcom running on linux to 115200 baudrate but it just receives some wrong characters. The app that I am running on the Pulpino is fpga_test app so it should continously transmit something over the uart. How is the baudrate set for Uart? In addition, I noticed that the spiloader app sets the clock frequency (configuration of the clk_wiz) to 5MHz. I would like to change that parameter, to set to 50MHz or any other but I assume there has to be some other change in sw code. I assume this also have impact on baud rate configuration. 

Any advice would be appreciated.

Thanks,
NK

Hello everyone,

i want the RISC-V GNU Compiler Toolchain to work on OS X. Here are my steps so far and what goes wrong.

Hi all,

I am planning to do some work on porting the Pulpissimo platform to several different FPGA boards. One will be Kintex KC705 and another one would Zynq ZC706. Potentially, there might also be a port to some of application specific boards, again, based on Kintex chip. 

I have run an out-of-box run for Zedboard just to get the feeling about the sizes of different iPs. One thing that I've noticed is that the clock frequency is set to 20MHz for the Zedboard and that the Vivado synthesis/implementation does report a fail in timing closure even for such a low clock frequency. 

My actual idea was to port to ZC706 and KC706 and to use a clock frequency of somewhere in the neighborhood of 80MHz-100MHz. 
Is this something that should be achievable? What would be a maximal achievable frequency for FPGA synthesis? 

In addition, have you been doing any synthesis runs for TSMC 40nm LP?

Thanks.

Cheers,
NK

Hi all, 

I am new to the forum and like to say Hi to all. I've been looking into using Pulpissimo platform in one of my projects that I am currently working on and would like to ask for some help. At the moment, I am at the very early stage of the project. My intention is use to use very basic subset of the Pulpissimo platform so I would like to start by removing some things that I don't need.

Is there an easy way of removing Hyperram interface from the udma subsystem? I would potentially also want to remove Cam interface and I2S interface. My project will, most likely, be using SPI and SDIO interfaces as well as uart. 

Thanks. 

If there is already a thread addressing this topic, please refer. 

Best 
Nemanja

Hello, team!

I am currently working on a project related to PULPino. I am wondering how to put the core in the IDLE state. The datasheet introduces an apb_event_unit for clock gating everything else and waking up the core if an event/interrupt arrives. I notice there is another peripheral, apb_pulpino contains CLK Gate as well. 
However, while running benchmarks such as hello/fft/sha/fir, I could not find the situations when the core is in the IDLE state. In other words, the clock signal is not gated during the entire operation. Is the clock gating function being enabled? Is there any benchmark I can use to test the clock gating (it would be better if the riscv-core and peripherals can be clock gated simultaneously)?

Thanks for your kind reply！

Hello, 

Just a quick question about the pulpissimo.

We implemented pulpissimo on the zcu102 board, and successfully ran some examples using SDK. We would like to ask if we have such "int a = {1,2,3,4};" array in the program, for example, in the hello test, where would the array be stored? Is that stored in the 8kb ROM, or 512kb L2?

We are asking this because we could successfully define the array under the size of 175, but when we defined the array with a larger size (e.g. a = {0,0,0,0,0,0,0,0......0}), the program will be stuck.

Thanks,
Zongru

Hello good members!
I've recently started working with pulp platform and ran MobileNet application available on both dory and pulp-sdk by following the instructions given on github. It was a successful test however i am not able to understand from where the input values are taken or generated and i wanted to modify the input image size and see the output. can anyone help me understand.

Hello

We are moving to pulp3 from pulp2 without the migration path. Setting all up in a container.
Using pulp/squeezer

Using the base_url from the created distribution, the web page displays three lines as below.
Inside Packages are directories [0-1a-z] and the packages are in there.


I was expecting a list of packages.
Are there a way to have the URL display the list of packages on one page?
Thanks so much.


base-url result:

• Packages/
  
• config.repo
  
• repodata/
  

Hi Experts,

I'm wondering, is the original Pulpissimo on git be able to boot Linux kernel? (with RI5CY I guess)
If not, how can I achieve it with minor changes? (like replacing RI5CY with Ariane). I'm expecting not to use certain platform like FPGA. It's like I'm going to boot up Linux in simulation with Pulpissimo (despite of speed)