|project|loc_Bangalore|loc_Pune|cat_s|cat_c|
|:------|:-----------:|:------:|:---:| ---:|
|abc    |1            |0       |0    |1    |
|Sys    |1            |0       |0    |1    |
|Syst   |0            |1       |1    |0    |
|EPS    |1            |0       |0    |1    |
|foss   |1            |0       |0    |1    |
|opc    |0            |1       |1    |0    |

> want list of projects,which should satisfy below condition:
   
 1. count of project related to loc_Bangalore <=3
 2. count of project related to loc_pune <=2
 3. count of project related to cat_c <=4
 4. count of project related to cat_s <=1
 5. total project selected <=5(final condition).

> whatever project will come in output it should fullfill all 5 condition.

I tried soe code:
 but not getting expected result.

    prob = LpProblem("choose project")
    project_list = list(df['project'])
    banglore = dict(zip(project_list,df['loc_Bangalore']))
    pune = dict(zip(project_list,df['loc_Pune']))
    c = dict(zip(project_list,df['cat_C']))
    s = dict(zip(project_list,df['cat_S']))
    proj_vars = pulp.LpVariable.dicts("project",project_list,cat='Binary')
    no_of_project_choose = 5
    prob += pulp.lpSum([banglore[f] * proj_vars[f] for f in project_list]) <= 3
    prob += pulp.lpSum([pune[f] * proj_vars[f] for f in project_list]) <=2
    prob += pulp.lpSum([c[f]  * proj_vars[f] for f in project_list]) <=4
    prob += pulp.lpSum([s[f]  * proj_vars[f] for f in project_list]) <=1
    prob += pulp.lpSum([[banglore[f] * proj_vars[f] for f in project_list]+[pune[f] * proj_vars[f] for f in project_list]+
         [c[f]  * proj_vars[f] for f in project_list]+[s[f]  * proj_vars[f] for f in project_list]]) <=5
    prob.solve()

> output:   abc 0.0,   sys 0.0,   syst None,   EPS 0.0 ,  foss 0.0 ,  opc
> None(i am getting all project with 0 or some number line abc 9)

Pls help me in solving this.I want only project which satisfy other condition also(like banglore, pune,c and s).
is there anyother way of solving this?
i m not sue about my solution and way of solving.plz help.

I've been looking at porting Tock OS on to the pulp platform and mostly reading through the documentation. I'm fairly new to this whole thing, so I have few questions. According to the TockOS porting guide, I need to define the following in the linker file

Quote: For most developers, it should
 * be sufficient to define {ROM/PROG/RAM}_{ORIGIN/LENGTH} (6 variables, the start and length for each),
 * MPU_MIN_ALIGN (the minimum alignment granularity supported by the MPU) and PAGE_SIZE (the size of a flash page).
 * If undefined, PAGE_SIZE uses the default value of 512 bytes.

Hi,

I ran the cv32e40p (RI5CY) core with FPU (floating point) enabled and tried to check the result for all the floating-point operations. I have faced the following issues in case of division and fused operations.

• Rounding mode output is incorrect for division, rounding mode for the division is not the same as addition, subtraction, and multiplication
  For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
  

• Exception status flags output is incorrect for division, exception status flags output for the division is not the same as addition, subtraction, and multiplication, and doesn't follow IEEE754
  For example, the overflow flag is not generated even if the division result generated is infinity (for MAX/MIN case).
  
• Rounding mode output is incorrect for fused operations, rounding mode for fused operations is not the same as addition, subtraction, and multiplication
  For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
  
• Getting output as X in fused operations if any of the operands is 0
  For example, If any of the 3 operands are 0 in FMA, the result generated by the core is X.
  

Hi,
   I notice in a lot of places in the entire pulpisismo code that contains ifndef depending upon the flag SYNTHESIS, I also notice ASIC_SYNTHESIS flag being used inside the Ri5cy.
I also find PULP_TRAINING flag in the code

 Example in soc_peripherals.sv

`ifdef PULP_TRAINING
`ifndef SYNTHESIS

    apb_dummy_registers  #(.APB_ADDR_WIDTH(APB_ADDR_WIDTH)) i_apb_dummy_reg_unit (
        .HCLK       ( clk_i                   ),
        .HRESETn    ( rst_ni                  ),
        .PADDR      ( s_apb_dummy_bus.paddr   ),
        .PWDATA     ( s_apb_dummy_bus.pwdata  ),
        .PWRITE     ( s_apb_dummy_bus.pwrite  ),
        .PSEL       ( s_apb_dummy_bus.psel    ),
        .PENABLE    ( s_apb_dummy_bus.penable ),
        .PRDATA     ( s_apb_dummy_bus.prdata  ),
        .PREADY     ( s_apb_dummy_bus.pready  ),
        .PSLVERR    ( s_apb_dummy_bus.pslverr )
    );

`endif
`endif

should these flags be passed through the synthesis as a macro ?

Hi,

I am very new to JTAG and have worked with pulpissimo by running test cases mostly via the Linux terminal, which has Questasimulation. 

I wanted to ask that how can I either create or locate an existing stimulifile, and further use it for JTAG programming? Also, which software would be good for JTAG programming?

Usually, when I make and run C-based test cases in the terminal, I am checking whether basic functions are working or not (since we are dealing with a constrained system and also my background is not very strong when it comes to architecture design-based projects). So if I run a test.c file using makefile, when using the command 'make clean all run' does this automatically create a stimulifile for this test.c somewhere in the directory? If yes, how can I locate it?
 
If not, how can create one for this test.c?



Thanks!

Hi,
I am working on various things related to GCC, e.g., LTO, GCC plugins etc. on Pulpissimo. To that end I have modified the contents of pulp-gcc-toolchain and pulp-sdk in the past. One thing that caused some problems was the linker option -nostdlib that's inserted by default by pulp-sdk to the generated makefiles. I always expected it to be absolutely necessary and did not scrutinize it further. However, when I simply tried to remove it everything still seems to remain working when running the binary in the FPGA.

So my question is... What's the rationale to use -nostdlib at all? It is included since the very last commit of pulp-sdk.
NB: The sdk also emits -nostartfiles too (which is implied by -nostdlib).

KR

Hello there!

I've been trying to generate the Bitstream of any board supported by you, but specifically, I want to generate for Nexys A7.

While trying this, I have the following error, after executing "$ make nexys rev=nexysA7-50T":

ERROR: [Vivado 12-172] File or Directory '/<my path>/pulpissimo/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci' does not exist
INFO: [Common 17-206] Exiting Vivado at Sun Apr 25 10:19:29 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/<my path>/pulpissimo/fpga/pulpissimo-nexys'
make: *** [Makefile:41: nexys] Error 2


I don't know if any Vivado license is required. I followed the README in GitHub, and after executing ./generate-scripts and ./update-ips, export certain env variables, and so on, there is the same issue. I am able to simulate pulpissimo in RTL simulations but in another computer that has QuestaSim license, and I am trying this bitstream generation in another one(that does not have QuestaSim), don't know if that is the problem. 

I tried other boards and it is the same issue.

Thanks for your answer!


EDIT: I realized that you updated the root GitHub with some changes regarding synthesis using Vivado 2020.2. I could fix the problem mentioned before by git pull command. But now, I got these errors:



Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/head_tail_q[0][free] has multiple drivers: i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_data_ffs[0].head_tail_q_reg[0][free]/Q, and i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_ht_ffs[0].head_tail_q_reg[0][free]/Q.

[...]
INFO: [Project 1-461] DRC finished with 16 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2950.625 ; gain = 64.703 ; free physical = 1185 ; free virtual = 7138
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 2 Warnings, 0 Critical Warnings and 17 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:17 2021...
[Mon Apr 26 11:39:17 2021] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:21 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/home/edgar/Documentos/proyecto_disenno_/pulpissimo/fpga/pulpissimo-genesys2'
make: *** [Makefile:8: genesys2] Error 2

It seems to be something related to this:

always @ (posedge CLK)
y = y + 1;
 
always @ (posedge CLK2)
y = y + 3;

[Reference]https://forums.xilinx.com/t5/Synthesis/ERROR-DRC-MDRV-1-Multiple-Driver-Nets/td-p/1025991

Thanks again!

I'm currently going through the training materials and I can't seem to run the hello world example. I get the following error message.

Quote:# Start time: 16:23:39 on Apr 21,2021
# ** Error: (vsim-3816) Optimized design "vopt_tb" cannot be used by this version of the simulator - it was only compiled for a 32-bit version of vsim
# Error loading design
Error loading design
# End time: 16:23:39 on Apr 21,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

Quote:Model Technology ModelSim SE vsim 10.7d Simulator 2019.02 Feb 15 2019

Hi,
   I am unable to run C code with printf statements using synthesized netlist. I have attached a simulation image of the stdout peripheral bus and FSM of Lint 2 AXI module. I notice that the C code runs successfully when no printf statements are given. 

The C code run when I get this issue is

#include <stdio.h>
int main()
{
  printf("Testing !\n");

  return 0;
}


Any thoughts on this issue?

Attached Files

Thumbnail(s)
   

Hi,
   I am trying to synthesize the pulpissimo, I don't find any documentation or specific script  for post-synthesis simulation but I have done the below steps

1) replaced the generic_memory, generic_rom with technology-related cells
2) synthesized soc_domain as top and have obtained synthesis netlist and its sdf file
3) I have replaced the soc_domain.sv with the synthesis netlist in sim/vcompile/rtl/pulpissimo.mk <-- all other files are same, not sure which files to keep and which one to remove 
3) I have added the CORE and CLK libs with -L option in sim/tcl_files/run.tcl

The modules gf2_fll , pulp_clock_gating , pulp_clock_mux2 , cluster_clock_gating , cluster_clock_inverter, pulp_clock_inverter are not synthesized, is any one these modules need to be synthesized for post-synthesis simulation?

what libraries should i need to keep in ./sim/tcl_files/config/vsim_ips.tcl ?

It will be great if someone can help me here

Vignajeth