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  Interrupt Service Routine for Pulpissimo
Posted by: RiscV - 02-22-2021, 09:09 AM - Forum: PULP General questions - Replies (2)

Hi,
Are there any documents or codes available to write Interrupt Service Routine for Pulpissimo in C language?

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  Getting input from console
Posted by: nayan - 02-19-2021, 05:33 AM - Forum: PULP General questions - Replies (3)

Scanf, gets, getchar etc. are showing undefined reference error while compiling a program using pulp-sdk. Is there anyway to get input from console?

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  how to simulate CV32E40P core
Posted by: gsaitejareddy - 02-08-2021, 08:11 AM - Forum: PULP General questions - Replies (2)

Hi,
I am trying to simulate CV32E40P core. In example_tb file in core folder there is a make file. It is showing error


vlib-"10.7b" work
/bin/sh: 1: vlib-10.7b: not found
make: *** [Makefile:87: .lib-rtl] Error 127

I read in the documentation that there is a separate repository for verification. I have run the makefile in core-v-verif/cv32/sim/core. i was able to run hello world program. But i dont why in CV32E40P core it was not running.

I wanted to explore floating point unit in CV32E40P core. Can you please say how to simulate with system verilog files

I am not able to understand how to give input to the core. Please help me

Thanks in advance

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  Question about bitstream generation
Posted by: zorrolee777 - 02-04-2021, 06:24 PM - Forum: PULP General questions - Replies (4)

Hi, I'm new to this and got some errors when generating the bitstream file.

The code I ran:

Code:
$ cd $COREVMCU/fpga
$ make clean_nexys rev=nexysA7-100T
$ make nexys rev=nexysA7-100T
After running the above codes, I got the following errors.
Code:
ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:48]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_slow_clk_gen' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:24]
ERROR: [Synth 8-6156] failed synthesizing module 'safe_domain' [/home/core-v-mcu/rtl/pulpissimo/safe_domain.sv:12]
ERROR: [Synth 8-6156] failed synthesizing module 'pulpissimo' [/home/core-v-mcu/rtl/pulpissimo/pulpissimo.sv:13]
ERROR: [Synth 8-6156] failed synthesizing module 'xilinx_pulpissimo' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v:22]


When I commented out the module, some other errors would come out, saying those modules are not found. I guess there're four of them, which are xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. I'm not sure if those modules are supposed to be generated by myself, or where should I get and put them? Any comments would be appreciated. Thanks in advance!

Sincerely,
Zorro

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  Compiling for RISCY without FP?
Posted by: LarsKeuninckx - 01-27-2021, 10:56 AM - Forum: PULP General questions - Replies (2)

I successfully got Pulpissimo with RISCY working on the Digilent ARTY-A7-100T board, running the "Hello" example using the pulp-SDK. Yeeey! Smile

I configured RISCY to not use a floating point unit, by setting:

Code:
localparam USE_FPU  = 0;

in xilinx_pulpissimo.v.

However, the gcc commands of the "Hello" example, following "make clean all", contain:

Code:
... -march=rv32imfcxpulpv2 -mfdiv ...


So the questions are: 
  • Does this mean floating point instructions are potentially still being generated?
  • If so, how do I make the toolchain aware that RISCY was configured without FP unit? Huh

Additional info: the toolchain was setup using the instructions at https://github.com/pulp-platform/pulp-ri...ation-pulp.


Thanks!

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  Failed at building the RTL simulation platform
Posted by: Jackie Zhang - 01-25-2021, 11:58 AM - Forum: PULP General questions - Replies (4)

Hi, All:
I followed the instruction to setup a simple run environment, but always failed at the build stage, with following messages:

** Error: ../ips/pulp_soc/rtl/pulp_soc/soc_interconnect.sv(22): Cannot find `include file "axi/assign.svh" in directories:

    ../ips/pulp_soc/../../rtl/includes, ../ips/pulp_soc/rtl/include, ../ips/pulp_soc/../axi/axi/include, /eda/Mentor/Questa10.7/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src, /eda/Mentor/Questa10.7/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src

I checked all cloned files, found AXI, dm, ... etc, NOT downloaded. 

Could you someone help me on this issue?

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  power efficient risc-v core
Posted by: limone - 01-21-2021, 11:20 PM - Forum: PULP General questions - No Replies

I read this interesting article- I do not know if this is an Ariane-like linux-capable core, but I am much more fascinated at its power efficiency at 1Ghz (or lower) than its 5ghz capabilities. 

https://www.eenewseurope.com/news/micro-...processor/ 

"Micro Magic details its 1GHz RISC-V processor core that consumes just 10mW when operated in the voltage-threshold region at 350mV.

Micro Magic in Sunnyvale, California, has already claimed that its RISC-V processor design was the fastest, but in an interview with eeNews Europe Mark Santoro, CEO of Micro Magic, said the processor core had also been designed so that it can operate down to at least 350mV, near the threshold voltage of the manufacturing process. "

"...However, the company has declined to say what manufacturing process or foundry manufacturer has been used. The company has said the design uses a FinFET process and that it examined physical design kits (PDKs) from three leading foundries seeking the broadest compatability before selecting one for manufacturing.

The process is likely to be somewhere between 20nm and 10nm and from one of Globalfoundries, Samsung, SMIC and TSMC."

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  pulp-rt-example Makefile and assembly code
Posted by: monniaux - 01-21-2021, 10:37 PM - Forum: PULP General questions - Replies (1)

What is the correct way to add assembly files (.s) to a project compiled with the Makefile system in the SDK?
Adding them to PULP_APP_FC_SRCS leads to strange errors.

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  simple runtime vs full SDK, when to use which one?
Posted by: LarsKeuninckx - 01-21-2021, 12:37 PM - Forum: PULP General questions - Replies (2)

Two questions regarding the SDK.
The readme at https://github.com/pulp-platform/pulpissimo says:

"We provide a simple runtime and a full featured runtime for PULPissimo. We recommend you try out first the minimal runtime and when you hit its limitations you can try the full runtime by installing the SDK."

1. What exactly are the limitations of the "simple runtime" vs the "full runtime SDK"? When to use which one?

2. How do you switch between the simple runtime and full runtime SDK? What is the proper way to uninstall the SDK? Just delete the pulp-sdk folder and git clone again?


Thanks!

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  Maximum frequency obtained when synthesizing the RI5CY core multiplier with 28 FD-SOI
Posted by: Olivier - 01-18-2021, 08:57 AM - Forum: PULP General questions - Replies (1)

Hello,

Out of curiosity, I'm learning more about the RI5CY core, especially the ex_stage. I read the Near-Threshold RISC-VCore With DSP Extensions for Scalable IoT Endpoint Devices paper and I got the core from the dedicated github page. Using Synopsys Design Compiler and the 28nm FD-SOI technology (the only technology available to me), I synthesized the multiplier (mult.sv) present in the RI5CY core. I obtain a maximum operating frequency of the multiplier of 200 MHz.

This frequency seems to me a little low. Considering the various documents I have seen on the internet, I would expect to obtain a frequency rather between 450 and 650 MHz.

Does anyone know if the maximum frequency of 200MHz is actually too low for the RI5CY core multiplier?


Thank you in advance.

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