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  Architecture file hierarchy
Posted by: bgeorge - 11-22-2022, 11:17 AM - Forum: PULP General questions - Replies (4)


I would like to deploy the pulp-platform in an Artix fpga but I don't know what files to include in the design and simulation, as well.
Are there any tree file which explains how the files are connected on RTL and Simulation level so that know which is the top level ?

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  Role of gapy, list of peripherals and capabilities of gvsoc
Posted by: nanoluka - 11-21-2022, 01:59 PM - Forum: PULP General questions - Replies (6)


getting acquainted with PULP platform these last few weeks - so, first of all, a big thank you and a bigger congratulations to all the creators and contributors.

I haven't had prior experience with tools such gvsoc, so I am bit troubled by trying to wrap my head around where are its limits, actually - hence this post. Please, any clarifications in this discussion would be of great help.

First of all, I've seen the videos from pulp training:

  1. Understanding and working with PULP
  2. GVSoC / Dory Tutorial
  3. A Deep Dive into HW/SW Development with PULP
and I've downloaded the VM and played a bit, followed along the steps demonstrated in the GVSoC/Dory video. All works great - I got the instructions dissasembled, saw the waveforms.

Now, I am getting confused with gapy... what is that, actually? It is mentioned, listed as a tool, but its purpose eludes me... I tried looking for other resources online, but I couldn't form a picture. At first, I though that's a python library that serves as a sort of a glue between the RTL pieces... at some point in the video, it is spoken about python generators... is that it?

In the next video (A deep dive...), I see that IP dependencies are treated using a tool called IPApprox, however - that was back then, while today this is the task of bender, if I am correct. However, where is this list of IPs? In the video, there's a subdirectory IPs of the pulpissimo repo, but I don't see it there: https://github.com/pulp-platform/pulpissimo

Finally, this gvsoc - if I am getting the idea correctly, it is a cycle-accurate simulator, meaning that it can simulate execution of RISCV instructions on a PULP hardware and yield dissasembled instructions, signal waveforms and metrics, such CPI. However, is it a stone carved thing, in the sense that it can simulate only a predefined configuration of pulpissimo SoC? In other words, can it be changed without QuestaSim so that simulates execution of a PULP program on an SoC configuration with SPI and without UART, say?

I think I am pretty sure that, if I want to add novel, arbitrary RTL, then I must have QuestaSim. But if I want to play with pulpissimo SoC configuration (adding or removing some of the existing peripherals), can this be done without QuestaSim, just using gvsoc? It seemed to me that the part where (in the lecture GVSoC tutorial) it is shown how to run with and without cluster is the response to this, but - I didn't get how to exclude uart and then include spi, for example?


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  Error during building RTL
Posted by: bgeorge - 11-18-2022, 10:49 AM - Forum: PULP General questions - Replies (3)


I get this error while I am trying to build the RTL.

~/workspace/pulp$ make scripts
curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \
    | bash -s -- 0.25.2
bender-init: Warning: No release for platform 'x86_64-linux-gnu-ubuntu22.04' version '0.25.2' found, using latest.
bender-init: Failed to download 'https://github.com/pulp-platform/bender/releases/download/v0.26.1/bender-0.26.1-x86_64-linux-gnu-ubuntu22.04.tar.gz'!
make: *** [Makefile:247: bender] Error 1

Can you please let me know what I am doing wrong ?


I must change the bash version in the Makefile.
bender: ifeq (,$(wildcard ./bender))    
curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \        
| bash -s -- 0.26.1    
touch bender endif

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  How to perform regression test when the compiler is replaced with LLVM
Posted by: lcx1092968411 - 11-15-2022, 07:43 AM - Forum: PULP General questions - No Replies

How to perform regression test when the compiler is replaced with LLVM, The compiler used by the existing regression test is GCC. I want to compile it with clang to run the regression test. Or, there are other test sets to test whether the clang compiler can correctly generate the instruction of pulp.

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  Custom extensions to the RISC-V ISA
Posted by: froggyhopper50 - 10-09-2022, 03:27 PM - Forum: PULP General questions - Replies (1)

Hello! I'm interested in creating custom extensions to the RISC-V ISA. The goal of these extensions would be to define instructions that perform specific operations (e.g., butterfly operations, twiddle factor generation, modular arithmetic) that I can use to implement various cryptographic primitives (e.g., NTT). I would then like to measure the speedup of these cryptographic primitives with my extensions enabled vs. with my extensions disabled.

What would be the best platform to achieve this goal?

I see one possibility, which is to take the CV32E40P core and extend it with custom functional units using SystemVerilog. I'd then have to find a way to get the compiler to take advantage of the new instructions that I've defined.

While I would be comfortable using SystemVerilog, I'm more interested in exploring the design space of possible instructions rather than attempting to debug a particular hardware design. For this reason, I'm curious if an architectural simulator / instruction set simulator would be more appropriate for my needs. Does PULP offer an architectural simulator / instruction set simulator? I found GVSoC, but I'm not sure if it's what I'm looking for.

Any advice would be greatly appreciated. Thank you!

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Posted by: giumaug - 09-29-2022, 08:09 AM - Forum: PULP General questions - Replies (1)

looking at website, I see several cores have been taped out.
I'm trying to find more info in how tape out has been carried out.
Is the tape out flow fully based on the RTL of the cores (the one available on GitHub repos) or human circuit customization has been
performed ?
For example, looking at https://github.com/openhwgroup/cv32e40p core I see the register file is described at high level as a simple array.
When it comes to circuit implementation has the synthesis  had free room to decide how to translate the RF in real digital circuit or some human
customization has been carried out?

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  Error run ./cmake_configure.riscv.gcc.sh
Posted by: Ali77124 - 08-25-2022, 05:00 PM - Forum: PULP General questions - No Replies

Hello, good time!

I'm going to run PULPino and i used ri5cy_gnu_toolchain for this.
But when using the ./cmake_configure.riscv.gcc.sh command, I get the following error:

C compiler identification is unknown
System unknown to cmake, create:
Platform/Linux-CXX To use this system, please send your configuration file to cmake@www.cmake.org so it can be added to cmake.
Your CMakeCache.txt file was copied to CopyOfCMakeCache.txt. Please send that file to cmake@www.cmake.org.
CMake error in CMakeLists.txt:20 (enable_language):
Tell CMake where to find the compiler by setting the environment
"CC" variable or CMake cache entry CMAKE_C_COMPILER to full path to
Compiler or named Compiler if it is in PATH.
The configuration is incomplete, errors have occurred!
See also "/home/ali/pulpino/sw/build/CMakeFiles/CMakeOutput.log".
See also "/home/ali/pulpino/sw/build/CMakeFiles/CMakeError.log".

Also, the PATH variable related to ri5cy as below in the bashrc file. I added:
export PATH=/home/ri5cy_gnu_toolchain/install/bin:$PATH
Thanks in advance for your help!

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  run PULPino on Ubuntu 20.04
Posted by: Ali77124 - 08-07-2022, 06:32 AM - Forum: PULP General questions - Replies (5)


I'm planning to run PULPino on Ubuntu 20.04 and started at https://github.com/pulp-platform/pulpino.

Do I need to use a specific gcc to run? Can you explain the steps involved in implementing this platform?

Thanks dear friends

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  QuestaSim Installation for RTL Simulation
Posted by: achen9 - 07-28-2022, 01:50 AM - Forum: PULP General questions - Replies (9)


I am new to RTL simulations, and I noticed that many of the PULP platforms appear to require QuestaSim in order to conduct them, but I am not too familiar with RTL environment setups. Specifically, I am currently working with HERO and Pulpissimo. 

I was wondering if anyone has any pointers or recommendations on where to look for instructions to set up a complete QuestaSim environment from scratch. The machine I am running on is CentOS 7.

Thank you very much in advance.

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Posted by: crazyfly1123 - 07-14-2022, 09:36 AM - Forum: PULP General questions - Replies (1)

Can I directly use mempool code on FPGA? Or where can I get a reference to use mempool, attached with mempool github link


Thank you in advance


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