hello，
I follow the steps at https://github.com/pulp-platform/pulp-sdk and want to create an SDK for PULPino. When I proceed to the "Target and platform selection" step, I want to find pulpino.sh in the config folder and source it, but I found that there is no such file. How should I build SDK for PULPino? Or does PULPino  need to build SDK?

hello，

My Linux distribution is Ubuntu 18.04. I followed the commands $ pip --version and $ python3 --version to check if the Python3 and pip3 versions match. The result is:

Lee@lee:~$ pip --version
Pip 9.0.1 from /usr/lib/python2.7/dist-packages (python 2.7)

Lee@lee:~$ python3 --version
Python 3.6.7

The results obtained seem to imply that the two versions do not match, but I have run the following commands to make them match:

$ sudo python3 -m pip install --upgrade pip
$ sudo python3 -m pip install artifactory twisted prettytable sqlalchemy pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

What is wrong with it?

PS: When I run pip3 --version, the result is:
Pip 19.0.3 from /usr/local/lib/python3.6/dist-packages/pip (python 3.6)

Hi,

there is no too much documentation in pulp-soc-defines.sv file. So could you clarify next statement:

// PE selection (only for non-FPGA - otherwise selected via PULP_CORE env variable)
// -> define RISCV for RISC-V processor
//`define RISCV

//PARAMETRES
`define NB_CLUSTERS   1
`define NB_CORES      8
`define NB_DMAS       4
`define NB_MPERIPHS   1
`define NB_SPERIPHS   8

-> Does this mean that in normal configuration there is 8 cores if?

When I tested gcc according to the "test suit" in the readme at https://github.com/pulp-platform/pulp-ri...-toolchain, after running the command "make check-gcc-newlib", it appeared  " /bin/sh: line 17: runtest: command not found",  is this problem serious? What is the reason, how to fix it?

hello，

When I compiled the toolchain according to the steps in https://github.com/pulp-platform/pulp-ri...-toolchain, I encountered the following error:
/tmp/ccIifWI0.s: Assembler messages:
/tmp/ccIifWI0.s:4963: Error: unrecognized opcode `lwu a1,.LANCHOR0 2'
/tmp/ccIifWI0.s:5179: Error: unrecognized opcode `lwu a5,.LANCHOR0'
/tmp/ccIifWI0.s:5258: Error: unrecognized opcode `lwu a4,.LANCHOR0 2'
/tmp/ccIifWI0.s:5905: Error: unrecognized opcode `lwu a2,.LANCHOR0 2'
/tmp/ccIifWI0.s:5997: Error: unrecognized opcode `lwu a3,.LANCHOR0 2'
/home/lee/Downloads/pulp-riscv-gnu-toolchain/riscv-gcc/libgcc/static-object.mk:17: recipe for target 'unwind-dw2.o' failed
Make[2]: *** [unwind-dw2.o] Error 1
Make[2]: Leaving directory '/home/lee/Downloads/pulp-riscv-gnu-toolchain/build-gcc-linux-stage1/riscv32-unknown-linux-gnu/libgcc'
Makefile:11207: recipe for target 'all-target-libgcc' failed
Make[1]: *** [all-target-libgcc] Error 2
Make[1]: Leaving directory '/home/lee/Downloads/pulp-riscv-gnu-toolchain/build-gcc-linux-stage1'
Makefile:150: recipe for target 'stamps/build-gcc-linux-stage1' failed
Make: *** [stamps/build-gcc-linux-stage1] Error 2

Since I am going to install the cross complier to /home/lee/Downloads/complier, so I run the commands below ：
1./configure --prefix=/home/lee/Downloads/complier --with-arch=rv32g --with-abi=ilp32d
2.make linux


 Is the install path chosen like this? Why is there such an error? How can I resolve these errors?

Hi, 

I am currently trying to use PULPissimo and the hello example runs fine, however when I try to run hwme example I got this error: 

" [/sys/board/chip/soc/fc/warning                   ] Invalid access (offset: 0x1a10c004, size: 0x4, is_write: 0)" 

Also Modelsim gui doesn't open when I use this command for hello example " make clean all run gui=1 " 

Can anyone passed this help in figuring out what's the problem ? 


Thanks in advance.

Hi, 

I am trying to build the "RISC-V GNU Compiler Toolchain" as a step for building the SDK for PULPissimio platform. When I try to execute the following command :

Hello，
I am a student  a complete novice in SOC design. Our tutor wants to implement a RISCV chip design on the extra area of the MPW. If I want to tape out PULPino, what should I verify first?

As far as I know, PULPino is a very mature project, and it has been taped out in different processes, so my current idea is:

1. Perform a Verilog simulation test. The assembly code of the instruction is compiled into a binary file to be read by Verilog's readmemh function, and then all instructions are tested one by one until all instructions pass the test. This part of the test should only involve the operation of the instruction set in the RISCY core.

2. Perform FPGA prototype verification on PULPino SOC. The purpose of this process is to download the SOC's Verilog code to the FPGA and then run the program on the FPGA. It may be necessary to use GDB and OpenOCD for debugging.

Is my idea correct? Does the PULPino project support the above two verifications? Can you give me some advice? And what should be noted in the tool chain, environment, SDK, etc.?

Thanks
zhouqiang

Hello,

I have been trying to Synthesize and implement Pulpissimo on Xilinx FPGA using Vivado . There are problems in the syntesized design although elaborated design seems to be Okay.  Have you synthesised Pulpissimo using VIvado and if yes then did you have to do changes to the RTL?

My synthesis basically is completed succesfully, but when I look at the synthesised schematics I can see that for example zynq_clk_i is not connected anywhere, although it should go to ref_clk_i in soc_domain.

Regards, Sirpa

Hello, 


I want to benchmark the performance of the 8 core multicore platform PULP. The current coremark example in pulp-rt-examples needs to be modified to be able to run it on PULP such that it uses the 8 cores of the cluster. Can a guideline be provided to modify the Coremark benchmark for the PULP platform. 

Regards,
Athena