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  PULPissimo Synthesis and Clock Distribution
Posted by: AhmedZaky - 11-20-2019, 06:55 AM - Forum: PULP General questions - Replies (1)

Hi all, 

First of all, thanks a lot for your help and support.

I was wondering if there is a synthesis - clean version of PULPissimo that's already released to the public. If not, is there any document / way to understand how the clock the distribution is going ? 

What I understand, correct me if I am wrong, that in the case of: 

1- FPGA, u r using a reference clock of 200 MHz to generate two internal clocks by divisions: A- Soc_clk = 20Mhz , B- periph_clk = 10Mhz.

2- In case of the RTL simulation, you r feeding from the TB a reference clock of ~ 32KHz and somehow, using DCO, FLL generating two clocks soc_clk = periph_clk = 17.5 MHz. 

If I am correct, are this on-chip clock generation modules synthesizable? Or they should be mapped to IPs in the PDK ? 

--------- 

Assuming that I want to drive the whole chip using the external clock, is it save to just remove all the " fll, DCO.. etc" modules and pass the signal through the modules to all the system components ? I mean the PAD_xtal_clk, pass it for the fc_subsystem, l2_memory .. etc and the system can work on that clock ? I already did simulation and it worked, but I am making sue that I didn't miss anything as I didn't test the system exhaustively. 

Thanks in advance.

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  Library Files
Posted by: mahalakshmir.ma - 11-15-2019, 10:19 AM - Forum: PULP General questions - Replies (6)

Hi,

I tried to include a new peripheral (PWM) into the PULPino environment, where can I get the library files for that peripheral or it will be auto generated.

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  Pulpissimo make error when making hello example
Posted by: bunohdwnl - 11-14-2019, 02:36 AM - Forum: PULP General questions - Replies (3)

Hello! I do the flow according to the Pulpissimo's README.md. But I meet a make error when I execute  the flow at the step "Downloading and running tests ".I change directory to  pulp-rt-examples/hello, and execute make clean all run ,then a "No Such File or Directory" error appears. I cat the Makefile,maybe the PULP_SDK_HOME is undefined. Do I need to set the PULP_SDK_HOME in my .bashrc  manually?

Code:
[jiaopy@localhost Jproject]$ cd pulp-rt-examples/hello/
[jiaopy@localhost hello]$ make clean all run
Makefile:6: /install/rules/pulp_rt.mk: No such file or directory
make: *** No rule to make target `/install/rules/pulp_rt.mk'.  Stop.
[jiaopy@localhost hello]$ cat Makefile
PULP_APP = test
PULP_APP_FC_SRCS = test.c
PULP_APP_HOST_SRCS = test.c
PULP_CFLAGS = -O3 -g
include $(PULP_SDK_HOME)/install/rules/pulp_rt.mk

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Question errors on building Linux cross-compiler
Posted by: mapletree - 11-12-2019, 09:16 PM - Forum: PULP General questions - Replies (5)

   
[attachment=15][attachment=15]
Hi,
I got some errors when build Linux cross-compiler with the following command:

Code:
./configure --prefix=/opt/riscv
make linux

The errors message is shown in the attached screenshot.
Anyone has an idea how to fix it?

Thanks!

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  Set defines of modules
Posted by: LPLA - 11-12-2019, 04:12 PM - Forum: PULP General questions - Replies (2)

Hello,

throughout the code you can find things like:

Code:
`ifdef QUENTIN_SCM
...
`endif

or

Code:
`ifndef PULP_FPGA_EMUL
...                              
`else
...
`endif

and there are two things about this that i just couldn't figure out.

First: Where are those defines? Let's say i want to use Quentin, where would i put `define QUENTIN_SCM (assuming this is the correct syntax).

Second: Assume i am having three different modules for multiplication mul1, mul2, mul3.
Every module has additional inputs if you want to do floating point multiplication.
This is handled by:
Code:
`ifdef FP_ENABLE
... (additional inputs)
`endif


I tested all three modules with Questasim using a testbench and created a .do file for them.
Now inside my .do file i have the following command:
Code:
set ms [concat mul1 mul2 mul3]
foreach m ${ms} {
  vlog -64 +define+FP_ENABLE ../multis/${m}/rtl/${m}.sv
}


If i now try to use my modules somewhere in PULPissimo i get some errors from my makefile that tell me some ports of the module are missing.
Basically the above command tells the modules mul1, mul2, mul3 that FP_ENABLE is defined and therefore the additional ports are instantiated.
Unfortunately i don't know how to use the same idea when trying to instantiate a mul-module in PULPissimo.
It is important to note that i don't want to change any line of code in the mul-modules!
Does anyone know a way how to tell the modules its defines just like the above command does?

Thank you.
LPLA

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  Ariane Performance Measures
Posted by: jthoma - 11-12-2019, 08:08 AM - Forum: PULP General questions - Replies (1)

Hi,

i am trying to do some performance measurements on the Ariane processor and therefore, I would like to use the cycle count from the RDCYCLE instruction. My code compiles fine, however, if I run it, I get a “illegal instruction” error. The following is the critical code snippet (both the CSRRS and RDCYCLE lead to the same error)


Code:
unsigned long get_clk(){
    unsigned long timer = 0;
    //__asm__ volatile("CSRRS %[result], cycle, x0\n\t" : [result]"=r"(timer)::);
    __asm__("RDCYCLE %[result]\n\t" : [result]"=r"(timer)::);
    return timer;
}

The RISC-V “Instruction Set Manual II: Privileged Architecture” states that the cycle CSR entry should be readable from user mode. I figured that this might not be the case in Ariane which would be fine if I could get to supervisor mode somehow. I looked into writing a kernel module that would give me access to the performance measures. Unfortunately, this turned out to be quite challenging since I can neither compile code on the FGPA nor use insmod to install my kernel module. Is there an easy way to get access to the cycle timer?

Thank you!

Jan

-- Edit: The same happens if I just use the built-in C time() function...

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  configparser module error when installing Pulpissimo SDK
Posted by: jmmarostegui - 10-28-2019, 01:50 PM - Forum: PULP General questions - Replies (9)

I have tried to install the Pulpissimo SDK, but without success. I have searched in the Forum for a similar problem, but I couldn't find it. Therefore, I'm posting here the sequence of commands I'm issuing and the final result. Any help will be appreciated.

I'm working on a clean Linux 16.04.06 Install. Following the information available in GitHub, here is the sequence I'm following:

1 - sudo apt install git python3-pip gawk texinfo libgmp-dev libmpfr-dev libmpc-dev swig3.0 libjpeg-dev lsb-core doxygen python-sphinx sox graphicsmagick-libmagick-dev-compat libsdl2-dev libswitch-perl libftdi1-dev cmake scons libsndfile1-dev

2 - sudo pip3 install twisted prettytable pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

3 - sudo pip3 install configparser

4 - cd /opt

5 - sudo mkdir riscv

6 - cd riscv

7 - git clone https://github.com/pulp-platform/pulp-ri...-toolchain

8 - cd pulp-riscv-gnu-toolchain

9 - git submodule update --init --recursive

10 - sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev

11 - sudo ./configure --prefix=/opt/riscv --with-arch=rv32imc --with-cmodel=medlow --enable-multilib

12 - make

13 - export PULP_RISCV_GCC_TOOLCHAIN=‘/opt/riscv’

14 - cd /opt/riscv

15 - sudo git clone https://github.com/pulp-platform/pulp-builder.git

16 - cd pulp-builder

17 - source configs/pulpissimo.sh

18 - sudo ./scripts/build-gvsoc

This last command fails with the following error:

...
make: Entering directory '/opt/riscv/pulp-builder/archi'
scons
scons: Reading SConscript files ...
ImportError: No module named configparser:
  File "/opt/riscv/pulp-builder/archi/SConstruct", line 4:
    import pulp_config as plpconfig
  File "/opt/riscv/pulp-builder/install/ws/python/pulp_config.py", line 23:
    import configparser
Makefile:2: recipe for target 'build' failed
make: *** [build] Error 2
make: Leaving directory '/opt/riscv/pulp-builder/archi'

I get exactly the same result if, instead of command 18 i issues the following three commands:

./scripts/clean
./scripts/update-runtime
./scripts/build-runtime

Since module configparser was apparently installed in step 3 I don't know what may be wrong.

Thank you very much in advance for your help.

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  Boot second partition on Ariane
Posted by: Jakob - 10-28-2019, 10:14 AM - Forum: PULP General questions - Replies (2)

Hello,
 
I try to run my own application (Hello.elf) inside a Linux system running on Ariane. The instantiation of Ariane and Linux was done according the description at the github page: https://github.com/pulp-platform/ariane.
 
According to this page https://github.com/pulp-platform/ariane-sdk/issues/25 the second partition on the SD card should be mounted at boot time, therefore, I just copied the binary into that partition. Unfortunately, I can't find the second partition.
 
During my search for a solution I found that Ariane repairs the GPT table of the SD card in such a way that fdisk detects the primary GPT table as corrupted, if the SD card is again inserted into my normal computer.
 
Below I post the output of fdisk before and after booting Linux on Ariane, as well as the part of the boot process, where the GPT is repaired.


Befor running Ariane (output at normal computer after running $ sudo sgdisk --clear --new=1:2048:67583 --new=2 --typecode=1:3000 --typecode=2:8300 /dev/sdb):
$ sudo fdisk -l /dev/sdb
Disk /dev/sdb: 29,7 GiB, 31914983424 bytes, 62333952 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: gpt
Disk identifier: B40F3443-EC5F-4185-8F91-C8E263A0DABA

Device     Start      End  Sectors  Size Type
/dev/sdb1   2048    67583    65536   32M ONIE boot
/dev/sdb2  67584 62333918 62266335 29,7G Linux filesystem

During the linux start on Ariane:
[   30.766351] GPT: Primary header thinks Alt. header is not at the end of the disk.
[   30.766351] GPT: Primary header thinks Alt. header is not at the end of the disk.
[   30.784484] GPT:62333951 != 62412799
[   30.784484] GPT:62333951 != 62412799
[   30.801305] GPT:Alternate GPT header not at the end of the disk.
[   30.801305] GPT:Alternate GPT header not at the end of the disk.
[   30.818495] GPT:62333951 != 62412799
[   30.818495] GPT:62333951 != 62412799
[   30.834014] GPT: Use GNU Parted to correct GPT errors.
[   30.834014] GPT: Use GNU Parted to correct GPT errors.
[   30.851527]  mmcblk0: p1 p2
[   30.851527]  mmcblk0: p1 p2

After running Ariane (output at normal computer)
$ sudo fdisk -l /dev/sdb
The primary GPT table is corrupt, but the backup appears OK, so that will be used.
Disk /dev/sdb: 29,7 GiB, 31914983424 bytes, 62333952 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: gpt
Disk identifier: B40F3443-EC5F-4185-8F91-C8E263A0DABA

Device     Start      End  Sectors  Size Type
/dev/sdb1   2048    67583    65536   32M ONIE boot
/dev/sdb2  67584 62333918 62266335 29,7G Linux filesystem

Any idea why the second partition is not recognised? Or more precisely, why the GPT table gets corrupted?


Thanks,
Jakob

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  Building pulp-toolchain for rv32ic and rv32emc
Posted by: mehrdad - 10-24-2019, 03:12 PM - Forum: PULP General questions - Replies (2)

Hi,
I am trying to use pulp-riscv-gnu-toolchain for Ibex (formerly Zero-riscy). The provided multi-lib covers rv32-ec and rv32-imc but rv32-ic and rc32-emc configurations are missing. I tried to build the toolchain specifically for these two configurations but so far with no success:

For rv32-ic I used:
./configure --prefix=... --with-arch=rv32ic --with-abi=ilp32 --with-cmodel=medlow
It compiled successfully, however the generated "libgcc.a" contained "mul" operations that resulted in "invalid instruction error" during RTL simulation.


For rv32-emc I used:
./configure --prefix=... --with-arch=rv32emc --with-abi=ilp32 --with-cmodel=medlow
The compilation failed:
--with-arch=rv32emc is not supported.  The argument must begin with rv32i, rv32g, rv64i, or rv64g.

Is there a way to compile for rv32-ic and rv32-emc?

Thanks and regards,
Mehrdad

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  Understanding the TCDM interconnect and implementing HWPEs
Posted by: LPLA - 10-22-2019, 01:03 PM - Forum: PULP General questions - Replies (4)

Hello,

I am currently trying to implement a HWPE into the PULPissimo platform.
Now i am facing a few problems and it would be great if someone could help me clarify some things.
This might be a rather long thread with quite a few questions but i hope that this will not only help me but also other people that (might) face the same or similar problems as i do.

What i am trying to do to understand the interaction between the L2 Memory, the TCDM interconnect and a HWPE, is to make my own simple HWPE.
At first it should only consist of a couple of registers and be able to read/write from/to the L2 Memory.
This means that data flow is the thing i am interested in at the moment.
If this simple HWPE works and can successfully read/write then a more complex HWPE can easily follow.


So first i was reading the HWPE Interface Specifications and the Systemverilog code to get a rough overview of the (possible) interactions between L2 Memory <-> TCDM <-> HWPE.
This is how i think things are working so please correct me if i am wrong:


There are (at least) two components that can do read/write operations on the L2 Memory.

First the core which has an instruction memory interface and a data memory interface.
The fc_subsystem has two XBAR_TCDM_BUS.Master ports used by the core.
One for data (l2_data_master) and one for instructions (l2_instr_master).
These connect the core with the XBAR_TCDM_BUS.Slave ports of the soc_interconnect_wrap.
The soc_interconnect itself then has a RISC data port and a RISC instruction port.
Now this is where things start to get more confusing to me.
But the important thing is that the core can use its data memory interface to interact with the L2 Memory.
This means i know that it is possible to send signals to the L2 Memory (req, addr, etc.) for read/write operations.
So one possibility would be to have the HWPE interact with the L2 Memory the same way the core does.
This brings up some question:
1) Can the core and the HWPE share the same bus? If yes, would that mean that the core would have to stall if the HWPE is using the bus?
2) If they don't share the same bus and you create a new connection to the L2 Memory based on the cores data memory interface, how could you handle possible errors regarding Write-After-Read, etc. I am not sure if the request/response trees are able to handle such scenarios as PULPissimo is a single core system. Then again there are also multi-core variants but i haven't read anything about data flow in such PULP systems.
3) Similar to 2) but this time the HWPE would use more than one port (similar to how the current HWPE implementation works).

The second component that can do read/write operations on the L2 Memory is the HWPE.
At least in the pulp-rt-example the data is loaded into the L2 Memory.
Now the HWPE uses streams and i tried to make my own HWPE use only one master port.
Questions regarding the HWPE variant:
1) Can you use a single port for read/write or do you need at least two (source+sink)?
2) I tried the pulp-rt-example for the accelerator and reduced the number of master ports down to two. This failed as it seems just changing the parameters for the number of master ports is not enough. You probably have to do some changes in the stream controller, right? (maybe even more changes)


So in a nutshell: I am trying to implement my own HWPE in a PULPissimo platform. Currently the HWPE should only be able to read/write from/to the L2 Memory. At first i wanted to use only one port for that. If that works i wanted to increase the number of ports.
The questions are:
- Does it make sense to use the same port as the core?
- Does it make sense to create a new port which mimics the port of the core?
- Would the best/easiest/most efficient way be to just use the ports of the HWPE which are already defined and just replace the example HWPE with my own?
- What are the limits of the number of ports for both the core style variant as well as the HWPE variant?


If anything is unclear please feel free to ask and i will try my best to give further details.


Thank you very much.
LPLA

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