The following warnings occurred:
Warning [2] Undefined variable $tcount - Line: 717 - File: portal.php PHP 8.3.8 (Linux)
File Line Function
/inc/class_error.php 153 errorHandler->error
/portal.php 717 errorHandler->error_callback
Warning [2] Undefined variable $tcount - Line: 722 - File: portal.php PHP 8.3.8 (Linux)
File Line Function
/inc/class_error.php 153 errorHandler->error
/portal.php 722 errorHandler->error_callback




Welcome, Guest
You have to register before you can post on our site.

Username
  

Password
  





Search Forums

(Advanced Search)

Forum Statistics
» Members: 379
» Latest member: divishas20
» Forum threads: 267
» Forum posts: 812

Full Statistics

Latest Threads
axi_xbar integration issu...
Forum: PULP General questions
Last Post: tbenz
07-16-2024, 09:30 AM
» Replies: 1
» Views: 74
issue with pulp build
Forum: PULP General questions
Last Post: kgf
07-03-2024, 08:46 PM
» Replies: 1
» Views: 183
i have some issue with si...
Forum: PULP General questions
Last Post: sungyong
06-17-2024, 04:03 AM
» Replies: 0
» Views: 186
Is there any RTL generato...
Forum: PULP General questions
Last Post: sungyong
06-17-2024, 03:55 AM
» Replies: 2
» Views: 381
install issue with pulpis...
Forum: PULP General questions
Last Post: sungyong
06-04-2024, 06:23 AM
» Replies: 3
» Views: 599
ELF Files for Polybench T...
Forum: PULP General questions
Last Post: kgf
05-24-2024, 11:38 AM
» Replies: 1
» Views: 336
OpenOCD Error with Nexys ...
Forum: PULP General questions
Last Post: NEO
04-25-2024, 06:26 AM
» Replies: 1
» Views: 1,596
Booting Pulpissimo from S...
Forum: PULP General questions
Last Post: kgf
04-25-2024, 06:19 AM
» Replies: 1
» Views: 386
how to manipulating of GP...
Forum: PULP General questions
Last Post: zealshah29
04-19-2024, 12:15 PM
» Replies: 6
» Views: 18,936
priviliged interrupts
Forum: PULP General questions
Last Post: tswaehn
04-16-2024, 01:43 PM
» Replies: 0
» Views: 345

 
  SPI Master
Posted by: istillaga - 10-19-2023, 08:34 AM - Forum: PULP General questions - Replies (2)

Hello i'm using Pulpino's SPI Master part to read a external sensor  that it is connected to one of the zedboard's pmod. I have configurated the spi_master_clkgen spi_clk polarity to start in 1. I have done the next code to read the sensor's id but I don't get any success:

#include <utils.h>
#include <stdio.h>
#include <spi.h>
#include <bench.h>
int main() {
    
  int sensor_id; 
    
    spi_setup_master(1);
  *(volatile int*) (SPI_REG_CLKDIV) = 0x2;


    spi_setup_cmd_addr( 0x0f, 8,0,0); 
    spi_set_datalen(8);
    spi_start_transaction(SPI_CMD_RD, SPI_CSN0);
    spi_read_fifo(&sensor_id, 8);
    printf(" LPS25HB sensor id: 0x%x\n", sensor_id);
    return 0;
}

Reviewing the signal with a logic a analizer I got this result: SCLK does as many clocks that spi_Reg_clkdiv value is, the chip select when CS is asserted, it remains asserted indefinitely. MOSI only does one pulse and MISO remains idle.

Anyone can help?

Print this item

  What is slm_conv-0.3 in HERO?
Posted by: ajgaspar - 09-08-2023, 06:08 PM - Forum: PULP General questions - Replies (3)

I'm trying to build the HERO project, and I am on the step where I am meant to run " ../test/gen_slm_files.sh <app_name>."
However, I have an issue with line 11 of the file, which is 

Code:
slm_conv=~andkurt/bin/slm_conv-0.3
When I try running the command, I am told that the directory above does not exist. "~andkurt" is obviously the creator's home directory, but what is slm_conv-0.3 and how can I install it? There's nothing in the github repo mentioning it, and I haven't found it referenced anywhere else on the PULP platform. Even on google I haven't found a relevant result.

Print this item

  HERO: Compiling OpenMP examples with only=pulp
Posted by: darbyshaw - 08-30-2023, 09:08 AM - Forum: PULP General questions - No Replies

Hello,

I am trying to compile the mm-small example in https://github.com/pulp-platform/hero/tr...s/mm-small. I would like to build it only for the PULP accelerator.
For that I run make only=pulp. I get the following error:

herov2/pulp/sdk/pkg/sdk/dev/install/include/archi/pulp.h:31:10: fatal error: 'archi/chips/PULP_CHIP_STR/pulp.h' file not found

Please could you help me identify the source of the problem.

Thank you!

Print this item

  Occamy Verilator simulation error
Posted by: pquanganh3105 - 06-14-2023, 03:24 AM - Forum: PULP General questions - Replies (2)

Dear sir,

I follow this instruction about Occamy: https://github.com/pulp-platform/snitch/...tem/occamy

However, when I ran command: make bin/occamy_top.vlt, I met this error:

%Error-PKGNODECL: occamy/snitch/hw/vendor/openhwgroup_cva6/core/include/ariane_rvfi_pkg.sv:20:17: Package/class 'riscv' not found, and needs to be predeclared (IEEE 1800-2017 26.3)

I recognize that your work-vlt/files lacks included file (it doesn't have snitch/hw/vendor/openhwgroup_cva6/core/include/riscv_pkg.sv so the simulator can not find package 'riscv') but whenever I ran the command above, work-vlt/files is automatically generated and it still remain lacking information.

How can fix that?

Many thanks

Print this item

  boot from external flash on genesys2 fpga
Posted by: a0000442 - 06-10-2023, 01:53 AM - Forum: PULP General questions - No Replies

hi
Can anyone tell me how to boot from external flash on geneysy2 fpga board in detail?
I use pulpissimo 7.0.0 and genesys2 fpga board.I can download app through openocd but
I cannot boot it from external flash.
I konw the step how to boot from flash
1. set the bootsel=2b00;
2. modify the bootrom.c in boot_code 
3. make and convert bootrom.c to fpga_bootrom.sv
4. rerun the fpga process and burn it
5. use plp_mkflash to convert app to flash.bin
6. burn flash.bin to external flash 
7.reset fpga and run app in flash
is it correct?
can anybody help me?how to modify bootrom.c in step2?

Print this item

  plp_mkflash cannot run
Posted by: a0000442 - 06-09-2023, 03:07 PM - Forum: PULP General questions - No Replies

When I use plp_mkflash in pulp-sdk/tools/runner/bin to make
flash.bin, the plp_mlflash tools display there is no module named “runner”
How can I solve it? I have build sdk successful.


I have download prebuilt pulp-sdk for Ubuntu 16 in GitHub and run the plp_mkflash tool.
It also cannot run and display no module named “runner”,what’s the matter with it?
help me! Sad

m



Attached Files Thumbnail(s)
   
Print this item

  Error building pulp sdk
Posted by: costola - 05-18-2023, 08:21 AM - Forum: PULP General questions - No Replies

I am stacked in installing the pulp-sdk.
First of all I have succesfully installed the pulp-rsicv-gnu-toolchain following the instruction on github https://github.com/pulp-platform/pulp-ri...-toolchain .
I performed the following step (I omit the part in which I install all the dependencies) :

1. $ git clone --recursive https://github.com/pulp-platform/pulp-ri...-toolchain

2. $ cd pulp-riscv-gnu-toolchain

3. $ export PATH=/opt/riscv/bin:$PATH

4. $ ./configure --prefix=/opt/riscv --with-arch=rv32imc --with-cmodel=medlow --
enable-multilib

5. $ make

Then I followed the instruction on github for what concern pulp-sdk https://github.com/pulp-platform/pulp-sdk .
I performed the following step (I omit the part in which I install all the dependencies) :

1. $ git clone https://github.com/pulp-platform/pulp-sdk

2. $ export PULP_RISCV_GCC_TOOLCHAIN=/opt/riscv

3. $ cd pulp-sdk

4. $ source configs/pulp-open.sh

5. $ make build

At step n°5 i have the following error:

Quote:cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo \

-DCMAKE_INSTALL_PREFIX=/home/luca/Desktop/Tesi/pulp-sdk/install/workstation \
-DGVSOC_MODULES="/home/luca/Desktop/Tesi/pulp-sdk/tools/gvsoc/common;/home/luca/Desktop/Tesi/pulp-sdk/tools/gvsoc/pulp" \
-DGVSOC_TARGETS=pulp-open
Re-run cmake no build system arguments
CMake Error: The source directory "/home/luca/Desktop/Tesi/pulp-sdk/build" does not exist.
Specify --help for usage, or press the help button on the CMake GUI.
Makefile:26: recipe for target 'build' failed
make: *** [build] Error 1

How can i solve ? It seems the build folder is missing.
I also checked this step by step installation guide https://www.pulp-platform.org/docs/pulp_..._part1.pdf

Print this item

  simulation qspi in FPGA
Posted by: HaiAnhWavelet - 05-10-2023, 09:32 AM - Forum: PULP General questions - Replies (1)

Hi, I'm trying run some tests about qspi in Genesy 2 broad but I have some problems. When run simulation with flash model, everything is good so I program it to my Kit. In genesys 2 have a qspi flash so I want to use it like a peripheral. In this reference, signals of qspi can connect via port in XDC file, expect qspi_sck. It must be connected via STARTUPE2. When I do so, it runs incorrectly. My test run through all code line but wave form in ocilloscope is different from Questasim.  Have anyone met this problem like that before?
Thanks

Print this item

  questions about fpga implemented of PULP
Posted by: Cruise Wang - 04-27-2023, 03:35 AM - Forum: PULP General questions - No Replies

We are trying to boot the PULP project whose original 8 riscv cores(ri5cy) have been replaced by 2 simd cores with 128bits datapath customized by us. We also replace the original HWPE with our customized systolic array. And we have successfully run RTL and Netlist systhesized by Design Compiler simulation. Now we are trying to boot it on our FPGA, but it seems we can boot the fc core(fabric controller) but fail to boot the cluster.
    We try to use gdb and openocd to debug step by step. It seems when the fc step into the cluster starting part, it's stuck. So we want to use gdb to connect our simd cores whose hart id are 0 and 1(the original 8 cores' hart id are 0-7, fc's hart id is 992(0x3e0),and we edit our jlink configuration file and add extra target create to trace the simd cores. But openocd reports it can't halt the core with id 0 and 1.
    So here are my questions:
    1、We would like to start a customized cluster. Are there any particular considerations or other methods that could help us with debugging? We welcome any suggestions you might have.
    2、For this heterogeneous kind of multicore system (one FC and two SIMD cores), how should we perform step-by-step debugging using GDB+OpenOCD? I would like to trace the FC and SIMD cores to see where exactly something went wrong. Or in other words, in the original PULP system, how should we go about debugging the 8 cores in the cluster and the FC core simultaneously?

Here's the jlink configuration file, we add extra target create to trace cores with id 0 and 1 but failed. Openocd reports it can't halt them.

Code:
proc init_targets {} {
    debug_level 2
    adapter speed 10000
    reset_config trst_only
    set _CHIPNAME riscv

    jtag newtap $_CHIPNAME unknown0 -irlen 5 -expected-id 0x10102001
    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
    # jtag newtap $_CHIPNAME cpu -irlen 5

    set _TARGETNAME $_CHIPNAME.cpu
    set _TARGETNAME0 $_CHIPNAME.fc
    set _TARGETNAME1 $_CHIPNAME.simd0
    set _TARGETNAME2 $_CHIPNAME.simd1
    # target create $_TARGETNAME riscv -endian little -chain-position $_TARGETNAME -coreid 0
    target create $_TARGETNAME0 riscv -endian little -chain-position $_TARGETNAME -coreid 0x3e0
        target create $_TARGETNAME1 riscv -endian little -chain-position $_TARGETNAME -coreid 0x0
        target create $_TARGETNAME2 riscv -endian little -chain-position $_TARGETNAME -coreid 0x1
   
    target smp $_TARGETNAME0 $_TARGETNAME1 $_TARGETNAME2
    # $_TARGETNAME configure -rtos riscv
    # $_TARGETNAME configure -work-area-phys 0x3ff0000 -work-area-size 0x10000 -work-area-backup 1
    # $_TARGETNAME riscv expose_csrs 3008-3015,4033-4034
}

gdb_report_data_abort enable
gdb_report_register_access_error enable



# prefer to use sba for system bus access
# riscv set_prefer_sba on

# dump jtag chain
scan_chain



init
halt
echo "Ready for Remote Connections"

Print this item

Wink Multi-cycle Path Handling in openPulp
Posted by: keran - 04-12-2023, 07:45 AM - Forum: PULP General questions - No Replies

Hi, 

Our team is currently working on taping out the "openPulp" design. We have synthesized the design using the Synopsys Design Compiler tool and performed Static Timing Analysis (STA) using Synopsys' Primetime. We noticed some peculiarities in the timing_max_normal_path.rpt report, which can be broadly categorized as follows: 

1.  Paths from CORE[0].ex_stage to another CORE.id_stage through FPNEW_UNIT,  with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/. 
   
2.  Paths from ex_stage to id_stage, with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/. 
   
3.  Paths related to the DFFs with the hwloop_regs_i_hwlp_counter_q_reg_ prefix in the id_stage. 
   
Additionally, we observed that signals such as mult_multicycle_i in the riscv_decoder module are annotated with comments like "//multiplier taking multiple cycles," as well as the apu_singlecycle and apu_multicycle signals. 

Our question is: Should the paths mentioned above be treated as multi-cycle paths or false path during synthesis? 

We would greatly appreciate any insights or guidance on this matter. 
Thank you in advance for your assistance. 
Best regards, 
[keran]



Attached Files
.pdf   PT timing report_openPulp.pdf (Size: 796.97 KB / Downloads: 2)
Print this item