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  questions about fpga implemented of PULP
Posted by: Cruise Wang - 04-27-2023, 03:35 AM - Forum: PULP General questions - No Replies

We are trying to boot the PULP project whose original 8 riscv cores(ri5cy) have been replaced by 2 simd cores with 128bits datapath customized by us. We also replace the original HWPE with our customized systolic array. And we have successfully run RTL and Netlist systhesized by Design Compiler simulation. Now we are trying to boot it on our FPGA, but it seems we can boot the fc core(fabric controller) but fail to boot the cluster.
    We try to use gdb and openocd to debug step by step. It seems when the fc step into the cluster starting part, it's stuck. So we want to use gdb to connect our simd cores whose hart id are 0 and 1(the original 8 cores' hart id are 0-7, fc's hart id is 992(0x3e0),and we edit our jlink configuration file and add extra target create to trace the simd cores. But openocd reports it can't halt the core with id 0 and 1.
    So here are my questions:
    1、We would like to start a customized cluster. Are there any particular considerations or other methods that could help us with debugging? We welcome any suggestions you might have.
    2、For this heterogeneous kind of multicore system (one FC and two SIMD cores), how should we perform step-by-step debugging using GDB+OpenOCD? I would like to trace the FC and SIMD cores to see where exactly something went wrong. Or in other words, in the original PULP system, how should we go about debugging the 8 cores in the cluster and the FC core simultaneously?

Here's the jlink configuration file, we add extra target create to trace cores with id 0 and 1 but failed. Openocd reports it can't halt them.

Code:
proc init_targets {} {
    debug_level 2
    adapter speed 10000
    reset_config trst_only
    set _CHIPNAME riscv

    jtag newtap $_CHIPNAME unknown0 -irlen 5 -expected-id 0x10102001
    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
    # jtag newtap $_CHIPNAME cpu -irlen 5

    set _TARGETNAME $_CHIPNAME.cpu
    set _TARGETNAME0 $_CHIPNAME.fc
    set _TARGETNAME1 $_CHIPNAME.simd0
    set _TARGETNAME2 $_CHIPNAME.simd1
    # target create $_TARGETNAME riscv -endian little -chain-position $_TARGETNAME -coreid 0
    target create $_TARGETNAME0 riscv -endian little -chain-position $_TARGETNAME -coreid 0x3e0
        target create $_TARGETNAME1 riscv -endian little -chain-position $_TARGETNAME -coreid 0x0
        target create $_TARGETNAME2 riscv -endian little -chain-position $_TARGETNAME -coreid 0x1
   
    target smp $_TARGETNAME0 $_TARGETNAME1 $_TARGETNAME2
    # $_TARGETNAME configure -rtos riscv
    # $_TARGETNAME configure -work-area-phys 0x3ff0000 -work-area-size 0x10000 -work-area-backup 1
    # $_TARGETNAME riscv expose_csrs 3008-3015,4033-4034
}

gdb_report_data_abort enable
gdb_report_register_access_error enable



# prefer to use sba for system bus access
# riscv set_prefer_sba on

# dump jtag chain
scan_chain



init
halt
echo "Ready for Remote Connections"

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Wink Multi-cycle Path Handling in openPulp
Posted by: keran - 04-12-2023, 07:45 AM - Forum: PULP General questions - No Replies

Hi, 

Our team is currently working on taping out the "openPulp" design. We have synthesized the design using the Synopsys Design Compiler tool and performed Static Timing Analysis (STA) using Synopsys' Primetime. We noticed some peculiarities in the timing_max_normal_path.rpt report, which can be broadly categorized as follows: 

1.  Paths from CORE[0].ex_stage to another CORE.id_stage through FPNEW_UNIT,  with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/. 
   
2.  Paths from ex_stage to id_stage, with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/. 
   
3.  Paths related to the DFFs with the hwloop_regs_i_hwlp_counter_q_reg_ prefix in the id_stage. 
   
Additionally, we observed that signals such as mult_multicycle_i in the riscv_decoder module are annotated with comments like "//multiplier taking multiple cycles," as well as the apu_singlecycle and apu_multicycle signals. 

Our question is: Should the paths mentioned above be treated as multi-cycle paths or false path during synthesis? 

We would greatly appreciate any insights or guidance on this matter. 
Thank you in advance for your assistance. 
Best regards, 
[keran]



Attached Files
.pdf   PT timing report_openPulp.pdf (Size: 796.97 KB / Downloads: 2)
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  Code examples in Assembly
Posted by: ivanhira - 04-11-2023, 07:14 PM - Forum: PULP General questions - Replies (1)

Hi, 

I'm trying to edit the address access on some parts of the code cause I may have to avoid using some CUTS of the L2 ram, and I cannot change the RTL as the design was already sent for tape-out. 
I'm not familiar with Assembly, but is it possible to get the code in Assembly and change the variables addresses to use only specific banks of the RAM? So far, I got the code from the command "make dis" but I think the code is formatted for debugging purposes, is there any command to get a working assembly code from the .c file?

Thanks in advance.

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  Post silicon analytics
Posted by: brownies - 03-21-2023, 09:29 AM - Forum: PULP General questions - Replies (1)

Hi
I'm a semiconductor specialist solutions architect, and I'm building an open-source post-silicon (yield) analytics solution. 
I'm hoping to partner with the PULP project, looking for parties that have taped-out an open-source chip, and have STDF files we can use to build this new tool...

Does the PULP project tape out chips? Is there a possibility to collaborate here?

Thanks,

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  OpenOCD Error with Nexys Video FPGA
Posted by: ivanhira - 03-13-2023, 06:36 PM - Forum: PULP General questions - No Replies

Hi, 

I'm trying to test Pulpissimo in Nexys Video FPGA, so far I can generate and load the bitstream to the FPGA, but when running OpenOCD, it shows the following error of "Debug Module did not become active. dmcontrol = 0x0"

Code:
ivantaka@ivantaka-pc:~$ sudo $OPENOCD/bin/openocd -f pulpissimo-caninos/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg -d
Open On-Chip Debugger 0.10.0+dev-00615-g2b6754e75 (2023-03-07-08:06)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
User : 13 1 command.c:544 command_print(): debug_level: 3
Debug: 14 1 options.c:184 add_default_dirs(): bindir=/home/ivantaka/pulpissimo-caninos/pulp-sdk/pkg/openocd/1.0/bin
Debug: 15 1 options.c:185 add_default_dirs(): pkgdatadir=/home/ivantaka/pulpissimo-caninos/pulp-sdk/pkg/openocd/1.0/share/openocd
Debug: 16 1 options.c:186 add_default_dirs(): exepath=/home/ivantaka/pulpissimo-caninos/pulp-sdk/pkg/openocd/1.0/bin
Debug: 17 1 options.c:187 add_default_dirs(): bin2data=../share/openocd
Debug: 18 1 configuration.c:42 add_script_search_dir(): adding /root/.openocd
Debug: 19 1 configuration.c:42 add_script_search_dir(): adding /home/ivantaka/pulpissimo-caninos/pulp-sdk/pkg/openocd/1.0/bin/../share/openocd/site
Debug: 20 1 configuration.c:42 add_script_search_dir(): adding /home/ivantaka/pulpissimo-caninos/pulp-sdk/pkg/openocd/1.0/bin/../share/openocd/scripts
Debug: 21 1 configuration.c:97 find_file(): found pulpissimo-caninos/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg
Debug: 22 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 1000
Debug: 23 1 command.c:143 script_debug(): command - adapter_khz ocd_adapter_khz 1000
Debug: 25 1 core.c:1645 jtag_config_khz(): handle jtag khz
Debug: 26 1 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 27 1 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 28 1 command.c:544 command_print(): adapter speed: 1000 kHz
Debug: 29 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_interface ftdi
Debug: 30 1 command.c:143 script_debug(): command - interface ocd_interface ftdi
Debug: 32 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_device_desc'...
Debug: 33 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_serial'...
Debug: 34 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_channel'...
Debug: 35 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_layout_init'...
Debug: 36 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_layout_signal'...
Debug: 37 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_set_signal'...
Debug: 38 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_get_signal'...
Debug: 39 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_vid_pid'...
Debug: 40 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_tdo_sample_edge'...
Debug: 41 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_oscan1_mode'...
Debug: 42 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_vid_pid 0x0403 0x6010
Debug: 43 1 command.c:143 script_debug(): command - ftdi_vid_pid ocd_ftdi_vid_pid 0x0403 0x6010
Debug: 45 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_channel 0
Debug: 46 1 command.c:143 script_debug(): command - ftdi_channel ocd_ftdi_channel 0
Debug: 48 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_init 0x0018 0x001b
Debug: 49 1 command.c:143 script_debug(): command - ftdi_layout_init ocd_ftdi_layout_init 0x0018 0x001b
Debug: 51 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nTRST -ndata 0x0010
Debug: 52 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nTRST -ndata 0x0010
Debug: 54 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 55 2 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Info : 56 2 transport.c:286 jim_transport_select(): auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Debug: 57 2 command.c:364 register_command_handler(): registering 'ocd_jtag_flush_queue_sleep'...
Debug: 58 2 command.c:364 register_command_handler(): registering 'ocd_jtag_rclk'...
Debug: 59 2 command.c:364 register_command_handler(): registering 'ocd_jtag_ntrst_delay'...
Debug: 60 2 command.c:364 register_command_handler(): registering 'ocd_jtag_ntrst_assert_width'...
Debug: 61 2 command.c:364 register_command_handler(): registering 'ocd_scan_chain'...
Debug: 62 2 command.c:364 register_command_handler(): registering 'ocd_jtag_reset'...
Debug: 63 2 command.c:364 register_command_handler(): registering 'ocd_runtest'...
Debug: 64 2 command.c:364 register_command_handler(): registering 'ocd_irscan'...
Debug: 65 2 command.c:364 register_command_handler(): registering 'ocd_verify_ircapture'...
Debug: 66 2 command.c:364 register_command_handler(): registering 'ocd_verify_jtag'...
Debug: 67 2 command.c:364 register_command_handler(): registering 'ocd_tms_sequence'...
Debug: 68 2 command.c:364 register_command_handler(): registering 'ocd_wait_srst_deassert'...
Debug: 69 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 70 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 71 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 72 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 73 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 74 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 75 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 76 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 77 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 78 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 79 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 80 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 81 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 82 2 command.c:364 register_command_handler(): registering 'ocd_svf'...
Debug: 83 2 command.c:364 register_command_handler(): registering 'ocd_xsvf'...
Debug: 84 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 85 2 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 86 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag newtap riscv unknown0 -irlen 5 -expected-id 0x10102001
Debug: 87 2 command.c:143 script_debug(): command - ocd_jtag ocd_jtag newtap riscv unknown0 -irlen 5 -expected-id 0x10102001
Debug: 88 2 tcl.c:550 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: unknown0, Dotted: riscv.unknown0, 4 params
Debug: 89 2 tcl.c:574 jim_newtap_cmd(): Processing option: -irlen
Debug: 90 2 tcl.c:574 jim_newtap_cmd(): Processing option: -expected-id
Debug: 91 2 core.c:1304 jtag_tap_init(): Created Tap: riscv.unknown0 @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 92 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag newtap riscv cpu -irlen 5 -expected-id 0x249511C3
Debug: 93 2 command.c:143 script_debug(): command - ocd_jtag ocd_jtag newtap riscv cpu -irlen 5 -expected-id 0x249511C3
Debug: 94 2 tcl.c:550 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 4 params
Debug: 95 2 tcl.c:574 jim_newtap_cmd(): Processing option: -irlen
Debug: 96 2 tcl.c:574 jim_newtap_cmd(): Processing option: -expected-id
Debug: 97 2 core.c:1304 jtag_tap_init(): Created Tap: riscv.cpu @ abs position 1, irlen 5, capture: 0x1 mask: 0x3
Debug: 98 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target create riscv.cpu riscv -chain-position riscv.cpu -coreid 0x3e0
Debug: 99 2 command.c:143 script_debug(): command - ocd_target ocd_target create riscv.cpu riscv -chain-position riscv.cpu -coreid 0x3e0
Debug: 100 2 target.c:1959 target_free_all_working_areas_restore(): freeing all working areas
Debug: 101 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 102 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 103 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 104 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 105 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 106 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 107 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 108 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 109 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 110 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 111 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 112 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 113 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 114 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 115 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 116 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 117 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 118 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 119 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 120 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 121 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 122 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 123 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 124 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 125 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 126 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 127 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 128 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 129 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 130 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 131 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 132 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 133 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 134 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 135 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 136 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 137 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 138 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 139 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 140 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 141 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 142 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 143 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 144 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 145 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 146 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 147 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 148 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 149 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 150 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 151 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 152 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 153 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 154 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 155 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 156 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 157 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 158 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 159 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu'...
Debug: 160 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_gdb_report_data_abort enable
Debug: 161 2 command.c:143 script_debug(): command - gdb_report_data_abort ocd_gdb_report_data_abort enable
Debug: 163 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_gdb_report_register_access_error enable
Debug: 164 2 command.c:143 script_debug(): command - gdb_report_register_access_error ocd_gdb_report_register_access_error enable
Debug: 166 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv set_reset_timeout_sec 120
Debug: 167 2 command.c:143 script_debug(): command - ocd_riscv ocd_riscv set_reset_timeout_sec 120
Debug: 169 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv set_command_timeout_sec 120
Debug: 170 2 command.c:143 script_debug(): command - ocd_riscv ocd_riscv set_command_timeout_sec 120
Debug: 172 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv set_prefer_sba on
Debug: 173 2 command.c:143 script_debug(): command - ocd_riscv ocd_riscv set_prefer_sba on
Debug: 175 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_scan_chain
Debug: 176 2 command.c:143 script_debug(): command - scan_chain ocd_scan_chain
User : 178 2 command.c:544 command_print():    TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
User : 179 2 command.c:544 command_print(): -- ------------------- -------- ---------- ---------- ----- ----- ------
User : 180 2 command.c:544 command_print():  0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
User : 181 2 command.c:544 command_print():  1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Debug: 182 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 183 3 command.c:143 script_debug(): command - init ocd_init
Debug: 185 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target init
Debug: 186 3 command.c:143 script_debug(): command - ocd_target ocd_target init
Debug: 188 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 189 3 command.c:143 script_debug(): command - ocd_target ocd_target names
Debug: 190 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu cget -event gdb-flash-erase-start
Debug: 191 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu cget -event gdb-flash-erase-start
Debug: 192 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 193 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 194 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu cget -event gdb-flash-write-end
Debug: 195 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu cget -event gdb-flash-write-end
Debug: 196 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 197 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 198 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu cget -event gdb-attach
Debug: 199 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu cget -event gdb-attach
Debug: 200 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu configure -event gdb-attach halt
Debug: 201 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu configure -event gdb-attach halt
Debug: 202 3 target.c:1421 handle_target_init_command(): Initializing targets...
Debug: 203 3 riscv.c:384 riscv_init_target(): riscv_init_target()
Debug: 204 10 semihosting_common.c:97 semihosting_common_init(): 
Debug: 205 10 command.c:364 register_command_handler(): registering 'ocd_target_request'...
Debug: 206 10 command.c:364 register_command_handler(): registering 'ocd_trace'...
Debug: 207 10 command.c:364 register_command_handler(): registering 'ocd_trace'...
Debug: 208 11 command.c:364 register_command_handler(): registering 'ocd_fast_load_image'...
Debug: 209 11 command.c:364 register_command_handler(): registering 'ocd_fast_load'...
Debug: 210 11 command.c:364 register_command_handler(): registering 'ocd_profile'...
Debug: 211 11 command.c:364 register_command_handler(): registering 'ocd_virt2phys'...
Debug: 212 11 command.c:364 register_command_handler(): registering 'ocd_reg'...
Debug: 213 11 command.c:364 register_command_handler(): registering 'ocd_poll'...
Debug: 214 11 command.c:364 register_command_handler(): registering 'ocd_wait_halt'...
Debug: 215 11 command.c:364 register_command_handler(): registering 'ocd_halt'...
Debug: 216 11 command.c:364 register_command_handler(): registering 'ocd_resume'...
Debug: 217 11 command.c:364 register_command_handler(): registering 'ocd_reset'...
Debug: 218 11 command.c:364 register_command_handler(): registering 'ocd_soft_reset_halt'...
Debug: 219 11 command.c:364 register_command_handler(): registering 'ocd_step'...
Debug: 220 11 command.c:364 register_command_handler(): registering 'ocd_mdd'...
Debug: 221 11 command.c:364 register_command_handler(): registering 'ocd_mdw'...
Debug: 222 11 command.c:364 register_command_handler(): registering 'ocd_mdh'...
Debug: 223 11 command.c:364 register_command_handler(): registering 'ocd_mdb'...
Debug: 224 11 command.c:364 register_command_handler(): registering 'ocd_mwd'...
Debug: 225 11 command.c:364 register_command_handler(): registering 'ocd_mww'...
Debug: 226 11 command.c:364 register_command_handler(): registering 'ocd_mwh'...
Debug: 227 11 command.c:364 register_command_handler(): registering 'ocd_mwb'...
Debug: 228 11 command.c:364 register_command_handler(): registering 'ocd_bp'...
Debug: 229 11 command.c:364 register_command_handler(): registering 'ocd_rbp'...
Debug: 230 11 command.c:364 register_command_handler(): registering 'ocd_wp'...
Debug: 231 11 command.c:364 register_command_handler(): registering 'ocd_rwp'...
Debug: 232 11 command.c:364 register_command_handler(): registering 'ocd_load_image'...
Debug: 233 11 command.c:364 register_command_handler(): registering 'ocd_dump_image'...
Debug: 234 11 command.c:364 register_command_handler(): registering 'ocd_verify_image_checksum'...
Debug: 235 11 command.c:364 register_command_handler(): registering 'ocd_verify_image'...
Debug: 236 11 command.c:364 register_command_handler(): registering 'ocd_test_image'...
Debug: 237 11 command.c:364 register_command_handler(): registering 'ocd_reset_nag'...
Debug: 238 11 command.c:364 register_command_handler(): registering 'ocd_ps'...
Debug: 239 11 command.c:364 register_command_handler(): registering 'ocd_test_mem_access'...
Debug: 240 11 ftdi.c:730 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 241 17 mpsse.c:429 mpsse_purge(): -
Debug: 242 21 mpsse.c:710 mpsse_loopback_config(): off
Debug: 243 21 mpsse.c:755 mpsse_set_frequency(): target 1000000 Hz
Debug: 244 21 mpsse.c:747 mpsse_rtck_config(): off
Debug: 245 21 mpsse.c:736 mpsse_divide_by_5_config(): off
Debug: 246 21 mpsse.c:716 mpsse_set_divisor(): 29
Debug: 247 21 mpsse.c:779 mpsse_set_frequency(): actually 1000000 Hz
Debug: 248 23 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 249 23 core.c:1615 adapter_khz_to_speed(): have interface set up
Debug: 250 23 mpsse.c:755 mpsse_set_frequency(): target 1000000 Hz
Debug: 251 23 mpsse.c:747 mpsse_rtck_config(): off
Debug: 252 23 mpsse.c:736 mpsse_divide_by_5_config(): off
Debug: 253 23 mpsse.c:716 mpsse_set_divisor(): 29
Debug: 254 23 mpsse.c:779 mpsse_set_frequency(): actually 1000000 Hz
Debug: 255 23 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 256 23 core.c:1615 adapter_khz_to_speed(): have interface set up
Info : 257 23 core.c:1394 adapter_init(): clock speed 1000 kHz
Debug: 258 23 openocd.c:142 handle_init_command(): Debug Adapter init complete
Debug: 259 23 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport init
Debug: 260 23 command.c:143 script_debug(): command - ocd_transport ocd_transport init
Debug: 262 23 transport.c:239 handle_transport_init(): handle_transport_init
Debug: 263 24 core.c:729 jtag_add_reset(): SRST line released
Debug: 264 24 core.c:753 jtag_add_reset(): TRST line released
Debug: 265 24 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 266 24 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init
Debug: 267 24 command.c:143 script_debug(): command - ocd_jtag ocd_jtag arp_init
Debug: 268 24 core.c:1407 jtag_init_inner(): Init JTAG chain
Debug: 269 24 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 270 26 core.c:1060 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 271 26 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 272 28 jep106.c:33 jep106_manufacturer(): BUG: Caller passed out-of-range JEP106 ID!
Info : 273 28 core.c:959 jtag_examine_chain_display(): JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : 274 28 core.c:959 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Debug: 275 28 core.c:1190 jtag_validate_ircapture(): IR capture validation scan
Debug: 276 28 core.c:1248 jtag_validate_ircapture(): riscv.unknown0: IR capture 0x05
Debug: 277 28 core.c:1248 jtag_validate_ircapture(): riscv.cpu: IR capture 0x05
Debug: 278 28 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_dap init
Debug: 279 28 command.c:143 script_debug(): command - ocd_dap ocd_dap init
Debug: 281 28 arm_dap.c:105 dap_init_all(): Initializing all DAPs ...
Debug: 282 28 openocd.c:159 handle_init_command(): Examining targets...
Debug: 283 28 target.c:1609 target_call_event_callbacks(): target event 17 (examine-start) for core 992
Debug: 284 28 riscv.c:916 riscv_examine(): riscv_examine()
Debug: 285 29 riscv.c:356 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1c71
Debug: 286 29 riscv.c:926 riscv_examine(): dtmcontrol=0x1c71
Debug: 287 29 riscv.c:928 riscv_examine():   version=0x1
Debug: 288 29 riscv-013.c:1701 init_target(): init
Debug: 289 30 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1c71
Debug: 290 31 riscv-013.c:1447 examine(): dtmcontrol=0x1c71
Debug: 291 31 riscv-013.c:1448 examine():   dmireset=0
Debug: 292 31 riscv-013.c:1449 examine():   idle=1
Debug: 293 31 riscv-013.c:1450 examine():   dmistat=3
Debug: 294 31 riscv-013.c:1451 examine():   abits=7
Debug: 295 31 riscv-013.c:1452 examine():   version=1
Debug: 296 31 riscv-013.c:259 get_dm(): [992] Allocating new DM
Debug: 297 32 riscv-013.c:393 scan(): 41b 0i w 00000000 @10 -> b 00000000 @10
Debug: 298 32 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 299 33 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 300 34 riscv-013.c:393 scan(): 41b 1i w 00000000 @10 -> + 00000000 @10
Debug: 301 34 riscv-013.c:393 scan(): 41b 1i - 00000000 @10 -> b 00000000 @10
Debug: 302 34 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 303 34 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 304 34 riscv-013.c:393 scan(): 41b 2i - 00000000 @10 -> + 00000000 @10
Debug: 305 36 riscv-013.c:393 scan(): 41b 2i w 00000001 @10 -> b 00000000 @10
Debug: 306 36 riscv-013.c:404 scan():  dmactive ->
Debug: 307 37 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 308 38 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 309 39 riscv-013.c:393 scan(): 41b 3i w 00000001 @10 -> + 00000000 @10
Debug: 310 39 riscv-013.c:404 scan():  dmactive ->
Debug: 311 40 riscv-013.c:393 scan(): 41b 3i - 00000000 @10 -> b 00000000 @10
Debug: 312 40 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 313 41 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 314 42 riscv-013.c:393 scan(): 41b 4i - 00000000 @10 -> + 00000000 @10
Debug: 315 44 riscv-013.c:393 scan(): 41b 4i w 07ffffc1 @10 -> b 00000000 @10
Debug: 316 44 riscv-013.c:404 scan():  hasel hartselhi=1023 hartsello=1023 dmactive ->
Debug: 317 44 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=5, ac_busy_delay=0
Debug: 318 46 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 319 49 riscv-013.c:393 scan(): 41b 5i w 07ffffc1 @10 -> + 00000000 @10
Debug: 320 49 riscv-013.c:404 scan():  hasel hartselhi=1023 hartsello=1023 dmactive ->
Debug: 321 50 riscv-013.c:393 scan(): 41b 5i - 00000000 @10 -> b 00000000 @10
Debug: 322 50 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=6, ac_busy_delay=0
Debug: 323 52 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 324 54 riscv-013.c:393 scan(): 41b 6i - 00000000 @10 -> + 00000000 @10
Debug: 325 56 riscv-013.c:393 scan(): 41b 6i r 00000000 @10 -> b 00000000 @10
Debug: 326 56 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=7, ac_busy_delay=0
Debug: 327 58 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 328 60 riscv-013.c:393 scan(): 41b 7i r 00000000 @10 -> + 00000000 @10
Debug: 329 62 riscv-013.c:393 scan(): 41b 7i - 00000000 @10 -> b 00000000 @10
Debug: 330 62 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=8, ac_busy_delay=0
Debug: 331 64 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 332 66 riscv-013.c:393 scan(): 41b 8i - 00000000 @10 -> + 00000000 @10
Error: 333 66 riscv-013.c:1486 examine(): Debug Module did not become active. dmcontrol=0x0
Debug: 334 66 openocd.c:161 handle_init_command(): target examination failed
Debug: 335 66 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash init
Debug: 336 66 command.c:143 script_debug(): command - ocd_flash ocd_flash init
Debug: 338 66 tcl.c:1222 handle_flash_init_command(): Initializing flash devices...
Debug: 339 66 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mflash init
Debug: 340 66 command.c:143 script_debug(): command - ocd_mflash ocd_mflash init
Debug: 342 66 mflash.c:1377 handle_mflash_init_command(): Initializing mflash devices...
Debug: 343 66 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_nand init
Debug: 344 66 command.c:143 script_debug(): command - ocd_nand ocd_nand init
Debug: 346 66 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...
Debug: 347 66 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_pld init
Debug: 348 66 command.c:143 script_debug(): command - ocd_pld ocd_pld init
Debug: 350 66 pld.c:205 handle_pld_init_command(): Initializing PLDs...
Debug: 351 66 gdb_server.c:3425 gdb_target_start(): starting gdb server for riscv.cpu on 3333
Info : 352 66 server.c:311 add_service(): Listening on port 3333 for gdb connections
Debug: 353 66 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_halt
Debug: 354 66 command.c:143 script_debug(): command - halt ocd_halt
Debug: 356 66 target.c:3059 handle_halt_command(): -
Error: 357 67 target.c:573 target_halt(): Target not examined yet
Debug: 358 67 command.c:651 run_command(): Command 'halt' failed with error code -4
User : 359 67 command.c:715 command_run_line():
Debug: 360 67 riscv.c:411 riscv_deinit_target(): riscv_deinit_target()
Debug: 361 67 riscv-013.c:1423 deinit_target(): riscv_deinit_target()
Debug: 362 67 target.c:1959 target_free_all_working_areas_restore(): freeing all working areas

I'm running this on Debian 10 VM on Virtualbox. It shouldn't be a problem as I did load the bitstream with the Vivado installed in the VM. Also the USB connection is visible with lsusb. 
I'm using pulpissimo releases 7.0.0 and the only change in RTL I've made is remove the FLLs as I didn't have the technology cells to synthesize it. In the simulation, the tests worked just fine after commenting init_fll in the SDK. 

Is there anything to be connected or changed in the RTL? What could be the problem and solution to this?

Thanks in advance.

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  Issues booting HERO in ZCU102
Posted by: pedro.lobo - 02-28-2023, 08:26 AM - Forum: PULP General questions - Replies (1)

Hello,

We are trying to get HERO running on a Xilinx ZCU102 board as per the project Readme instructions. We've got to the point of trying to boot the host processor but a kernel panic occurs afther the error: "Unable to handle kernel paging request at virtual address ffffffc078000001", as can be seen in the attached log. Chan someone shed some light on this?

The Readme instructions say that "On the first boot, change the U-Boot variables as described in issue #107", but strangely there is no "Issues" tab on the HERO Github repository so we don't know if our issue is related with that variable change.

Thank you in advance. Best regards,

Pedro Lobo.



Attached Files
.txt   uboot-log-01.txt (Size: 13.5 KB / Downloads: 0)
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  Which SDK to be used to compile applications for FPGA nowadays?
Posted by: AhmedZaky - 02-27-2023, 01:09 PM - Forum: PULP General questions - No Replies

Hi, 

Earlier I used SDK V1 to compile C codes to run over FPGAs, however, I used it with an older version of the RTL. Many changes have been made to the RTL and a new SDK version has been released. 

However, the new SDK doesn't have instructions on how to compile applications for FPGA targets neither I see the same directory structure as the old one.

When I used the V1 SDK to compile the application to run over the Nexys A7 using the new RTL, I faced this issue: 

Quote:19 #include <stdio.h>

20 #include <rt/rt_apt.h>

22 int __rt_fpga_fc_frequency = 10008000; // e.g. 10000800 for 10MHZ;
23 int __rt_fpga_periph_frequency = 5000000; // e.g. 5000000 for SMHZ;
24
(gdb) list

26 int main()

27 {

28 while (1) {

29 printf("Hello World!\n\r");

30 for (volatile int i=6; 1<1000008; i++);

31 }

2 return 0;

(gdb) continue

Continuing.

^c

Program received signal SIGINT, Interrupt.
0x1c009452 in __rt_exit_debug_bridge (status= -1)  at libs/i0/10.c:560
 __rt_bridge_clear_notif();

Please advise, thanks!

Also, when I connect GDP with the OPENOCD, I get the following message:

Target-supplied registers are not supported by the current architecture 0x1a000080 in ?? ()

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  Debug the simulated code
Posted by: angramemnos - 02-24-2023, 09:12 AM - Forum: PULP General questions - Replies (2)

Hello forum,

I want to ask if there is any way to debug the C code that is running on the pulp-runtime. The solutions that I find (pulp-debug-bridge, openocd and gdb)  works with pulp-sdk and as far I know the sdk is no longer working. Thank you for helping.

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  Can I remap Pulpissimo pads to connect a camera on Genesys2 fpga board?
Posted by: tparng - 01-07-2023, 02:11 PM - Forum: PULP General questions - Replies (2)

Hi,

I want to connect a camera to Pulpissimo's Camera Interface (CPI) on Genesys2 board.  However, most CPI pads are connected to LEDs/buttons/switches on Genesys2 board.  Can I modify the constraints file to remap and connect the CPI signals to the FMC connector so that I can use Digilent FMC Pcam Adapter to connect camera modules?  Any considerations I need to take ?

Thanks,

tparng

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  Latest Pulpissimo RTL doesn't fit the nexysA7-100T FPGA
Posted by: AhmedZaky - 01-05-2023, 01:40 PM - Forum: PULP General questions - Replies (3)

Hi, 

I have been trying to program Nexys A7 with the latest Pulpissimo RTL and I am encountering these issues, any clue? 


  1. REPORT DETAILS

UTLZ-1#1 Error
Resource utilization - PBlock:ROOT
RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 288 of such cell types but only 270 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#2 Error
Resource utilization - PBlock:ROOT
RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#3 Error
Resource utilization - PBlock:ROOT
RAMB36E1 over-utilized in Top Level Design (This design requires more RAMB36E1 cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:



Regards,

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