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  [PULPissimo] How to resize memory correctly
Posted by: gideros - 12-16-2019, 02:21 AM - Forum: PULP General questions - No Replies

Hi,

I'm working on a design based on PULPissimo and we're about to tape-out a test chip. But the technology that we're working on is pretty "big" (HC90L from SK Hynix), thus 512KB of total memory takes way too much area. Therefore I wanna reduce the total size of memory into half (256KB). 

In order to do that, I modified these:
- pulp_soc.sv (half size for both L2_BANK_SIZE and L2_BANK_SIZE_PRI).
- fpga_settings.mk (for a test build on FPGA)
- soc_interconnect.sv (for memory address, reduce PER_END_ADDR of PRI_L2_CH1, PRI_L2_CH0 and TCDM_END_ADDR).
- pulp-configs/configs/chips/pulpissimo/pulpissimo.json (memory size for sdk I guess)
The result is pretty bad. Simulation shows lots of "a request with unknown address". I guess I was wrong somewhere, or missed something.

And  since I disable FPU to reduce SoC size (I don't really need it), I also change ri5ky_v2_fpu_1_10 to a custom core that doesn't have FPU arguments.
-   "isa" from "rv32imfcXpulpv2" to "rv32imcXpulpv2"
- Remove "--fpu", "--fpud" and "--shared-fpu" from "gv_isa"
- Remove "compiler_args"
Eventhough, the final binary generated by SDK still has FPU related instruction, which will resulted in "Illegal instruction" exception while execute the program. 

Can you please help me out with above issues? Thank you very much in advance.
Regards.

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  ubuntu 16.04
Posted by: cello - 12-15-2019, 09:04 AM - Forum: PULP General questions - Replies (2)

Hi, can I use ubuntu 16.04 LTS application on windows10 to install files from pulp platform? Or do I need completely ubuntu operating system on my pc?

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Question [Pulpissimo]where are the <board_target>.sh ?
Posted by: bunohdwnl - 12-13-2019, 07:41 AM - Forum: PULP General questions - Replies (6)

Hello, in the  Pulpissimo's README.md,it says 

Quote:Supported Boards
At the moment the followin g boards are supported:

  Digilent Genesys2
  Xilinx ZCU104
  Xilinx ZCU102
  Digilent Nexys Video
  ZedBoard

  
  In the  section  Compiling Applications for the FPGA Target, it  says  

Quote:To run or debug applications for the FPGA you need to use a recent version of the PULP-SDK (commit id 3256fe7 or newer.'). Configure the SDK for the FPGA platform by running the following commands within the SDK's root directory:

  source configs/pulpissimo.sh
  source configs/fpgas/pulpissimo/<board_target>.sh
 
 Question:   When I git clone the pulp-sdk.git and changed directory to  pulp-sdk/configs/fpgas/pulpissimo/, I  only found the genesys2.sh. Now I am using Digilent Nexys Video Board, but there is no nexys_video.sh . What should I do?

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  UART
Posted by: HariniM - 12-12-2019, 09:12 AM - Forum: PULP General questions - No Replies

Hi,

I am trying to run the UART testcase already available one(path - sw/apps/imperio_tests/testUART). The simulation runs forever and it is not even entering the main of the C program. I followed the same steps for the I2C, I am able to run I2C but not UART. Could anyone help me on the same. 

I am wondering how the test cases are routed to tb/rtl. Can anyone explain the flow.

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  PWM peripheral integration in PULPino
Posted by: HariniM - 12-12-2019, 07:54 AM - Forum: PULP General questions - Replies (1)

Hi,

I integrated PWM into PULPino via APB interface. I need to drive PWM signals from TB. Can anyone help me how to drive signals from tb?

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  questasim test case failed
Posted by: mahalakshmir.ma - 12-06-2019, 04:03 AM - Forum: PULP General questions - No Replies

hi,
 
I tried running interfaced GPIO with the test cases given in PULPino environment. after running testcases I am getting has test case  failed. why test failed occurs.

** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_RXFF
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_TXFF
# Using MEMLOAD method: PRELOAD
# Using      ri5cy core
# [SPI] Enabling QPI mode
# [adv_dbg_if] AXI4 WRITE         32 burst @1a107008 for           4 bytes.
# Preloading memory
# Preloading instruction memory from slm_files/l2_stim.slm
# Preloading data memory from slm_files/tcdm_bank0.slm
# [TRACER] Output filename is: trace_core_00_0.log    
#[SPI] Received 00000003
#[SPI] Test  Failed
# **Note :$Stop   


THANKS IN ADVANCE   

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  Compiling and running application on Zedboard (Pulpissimo)
Posted by: jmmarostegui - 12-05-2019, 01:25 PM - Forum: PULP General questions - Replies (3)

Good afternoon,

After several issues I have been able to install the complete SDK and platforms. 

I'm able to compile applications and run them on the rt platform. I'm also able to complete the Vivado implementation of Pulpissimo for the Zedboard. However, I'm still not able to run applications on the Zedboard.

The sequence of steps I carry out are:

1 - Using Vivado Hardware manager I program the device on the Zedboard with the pulpissimo-zedboard.bit configuration file. Everything is fine, the device is configured and led LED0 is on (from the .xdc file and xilinx_pulpissimo.v I identify that this is CSN for SPI channel 1, so it is OK).

2 - source configs/pulpissimo.sh

3 - source configs/fpgas/pulpissimo/genesys2.sh (from the information provided in GitHub there shoulb be also a zedboard.sh script, but this is the only one that can be found)

4 - source sourceme.sh

5 - make clean all

6 - The USB cable that was used to configure the Zynq device is removed from the Zedboard.

7 - The Digilent JTAG-HS2 cable is attached to PMOD A.

8 - openocd -f openocd-zedboard-hs2.cfg

9 - riscv32-unknown-elf-gdb FILENAME

10 - (gdb) target remote localhost:3333

11 - (gdb) load

If within gdb I issue two list commands here is what I get:

1 /*
2 * This example shows how drive a GPIO as an output.
3 */
4
5 #include <stdio.h>
6 #include <rt/rt_api.h>
7 #include <stdint.h>
8
9 #define GPIO 20
10
(gdb) list
11 int __rt_fpga_fc_frequency = 20000000; // e.g. 20000000 for 20MHz;
12 int __rt_fpga_periph_frequency = 10000000; // e.g. 10000000 for 10MHz;
13
14 int main()
15 {
16  unsigned long i;
17
18  // First configure the SPI device
19  rt_spim_conf_t conf;
20  // Get default configuration

Now I want to place a breakpoint at line 19. Therefore what I get is:

(gdb) b 19
No line 19 in the current file.
Make breakpoint pending on future shared library load? (y or [n]) 

Therefore, it seems that something is wrong. If I issue the command 'continue' on gdb I get the message Continuing, and nothing happens.

I have tried the same flow, but issuing a 'source platform-fpga.sh' after step 4, but the result is the same.

Can you identify if something is missing or wrong in the steps I'm following? Any help will be appreciated.

In order to check if the program is being executed properly by Pulpissimo on the Zedboard I'm trying to turn OFF LED0 by changing the value of the CSN signal of SPI channel 1 that is mapped onto this LED, but without success until now.

Best regards,

Manuel

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  UART test case
Posted by: mahalakshmir.ma - 12-05-2019, 08:01 AM - Forum: PULP General questions - Replies (2)

Do anyone try running UART testcase(already available testUART.c) in PULPino?

I tried it but the simulation never ends, why so?. can anyone help me on this 

I am getting the following in my transcript window

** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_RXFF
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_TXFF
# Using MEMLOAD method: PRELOAD
# Using      ri5cy core
# [SPI] Enabling QPI mode
# [adv_dbg_if] AXI4 WRITE         32 burst @1a107008 for           4 bytes.
# Preloading memory
# Preloading instruction memory from slm_files/l2_stim.slm
# Preloading data memory from slm_files/tcdm_bank0.slm
# [TRACER] Output filename is: trace_core_00_0.log

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  waves
Posted by: mahalakshmir.ma - 11-29-2019, 10:28 AM - Forum: PULP General questions - Replies (1)

hi

How to see waveforms in questasim while running the given testcases. I tried to add the signals to waveform window, but I am not able to do it. Is there any command available?.

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  Problem installing PULP-SDK
Posted by: jmmarostegui - 11-27-2019, 12:49 PM - Forum: PULP General questions - Replies (7)

Hello,

I'm trying to install PULP-SDK following the instructions provided in GitHub, but I get an error I can't understand and for which I haven't found any solution.

I'm starting from a clean Ubuntu 16.04 install, and the sequence of steps I follow (first I install the riscv gnu toolchain and then the PULP SDK) is:

1 - sudo -s

2 - apt install git python3-pip python-pip gawk texinfo libgmp-dev libmpfr-dev libmpc-dev swig3.0 libjpeg-dev lsb-core doxygen python-sphinx sox graphicsmagick-libmagick-dev-compat libsdl2-dev libswitch-perl libftdi1-dev cmake scons libsndfile1-dev

3 - pip3 install artifactory twisted prettytable sqlalchemy pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

4 - sudo pip2 install configparser

5 - cd /opt

6 - mkdir riscv

7 - cd riscv

8 - git clone https://github.com/pulp-platform/pulp-ri...-toolchain

9 - cd pulp-riscv-gnu-toolchain

10 - git submodule update --init --recursive

11 - apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev

12 - export PATH=$PATH:/opt/riscv/bin

13 - ./configure --prefix=/opt/riscv --with-arch=rv32imc --with-cmodel=medlow --enable-multilib

14 - make

15 - export PULP_RISCV_GCC_TOOLCHAIN=/opt/riscv

16 - export VSIM_PATH=/opt/riscv/pulpissimo/sim

17 - cd ..

18 - git clone https://github.com/pulp-platform/pulp-sdk.git -b master

19 - cd pulp-sdk

20 - source configs/pulpissimo.sh

21 - make all

After this last command I get the following error:

Configuring Pulp project at /opt/riscv/pulp-sdk
Traceback (most recent call last):
  File "./pulp-tools/bin/plpbuild", line 3, in <module>
    import plptools as plp
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plptools.py", line 27, in <module>
    from plpobjects import *
  File "/opt/riscv/pulp-sdk/pulp-tools/bin/plpobjects.py", line 32, in <module>
    from openpyxl import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/__init__.py", line 6, in <module>
    from openpyxl.workbook import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/workbook/__init__.py", line 4, in <module>
    from .workbook import Workbook
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/workbook/workbook.py", line 7, in <module>
    from openpyxl.worksheet.worksheet import Worksheet
  File "/usr/local/lib/python3.5/dist-packages/openpyxl/worksheet/worksheet.py", line 392
    return f"{get_column_letter(min_col)}{min_row}:{get_column_letter(max_col)}{max_row}"
                                                                                        ^
SyntaxError: invalid syntax
Makefile:6: recipe for target 'all' failed
make: *** [all] Error 1

Following the instructions provided in GitHub I check the versions of both python and pip. What I get is:

root@VBox:/opt/riscv/pulp-sdk# pip --version
pip 19.3.1 from /usr/local/lib/python2.7/dist-packages/pip (python 2.7)
root@VBox:/opt/riscv/pulp-sdk# python3 --version
Python 3.5.2

Then I execute the commands suggested in GitHub:

python3 -m pip install --upgrade pip
python3 -m pip install artifactory twisted prettytable sqlalchemy pyelftools openpyxl xlsxwriter pyyaml numpy configparser pyvcd

However, when I run again 'make all' I get the same error. Since after looking for a solution I haven't found any clue how to fix it, could you provide me any hint to overcome this problem? Thank you very much in advance for your help.

Best regards,

Manuel

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