I'm trying to synthesize PULPissimo using Genus Synthesis Solution. But it is showing a lot of errors and warning about unsynthesizable codes on read_hdl -sv command (e.g., class declaration, @(posedge )), and some errors about attributes which in this case, after reading a bit about, I ignored when they were warnings or deleted when they were errors.
The code was made to be synthesizable, i guess, right? The problem might be in the old version of Genus that I'm using in the server (version 16.20), but are those examples (class declaration and @(posedge)) supported in the new version of Genus?
Also, I've defined the macros SYNTHESIS and ASIC_SYNTHESIS just in case when running read_hdl, though that didn't seem to solve any of the error showed. Are there any more macros needed for the synthesis?
I attached the log of the read_hdl command, showing all the warnings and errors.
Did anybody check that the PULP platform (in general, I mean several projects) SystemVerilog compiles with Intel FPGA Quartus toolchain ?
I tried with cvfpu and did not work for me. Maybe I missed something, but I had the impression that you are using some SystemVerilog features not supported by Quartus Prime (v. 21.1).
I am interested in implementing Opentitan on a cheap FPGA. The reference board, CW310, is very expensive. Can cheap FPGAs such as Tang nano 9k, ICE40, ECP5, etc' be used? My preference is to use open-source tools as much as possible. Perhaps these FPGAs don't have enough resources for the whole Opentitan and only a partial implementation is possible!? I would appreciate any comments/recommendations.
I am new to the cva6, and I have a project to extend the functionality of the cva6 tlb.
In order to do so, I plan to create a testbench and compile the tlb module
to validate the current and extended functionalities. However, I am stuck at the
compilation step to compile only the tlb module and its related modules/files.
I would be appreciated if someone would suggest a starting point to accomplish such task?
I'm trying to simulate Pulpissimo using the test examples from pulp-rt-examples. I'm using the releases v7.0.0 of Pulpissimo, with some modifications at pad_control.sv fixing the mux indexes for the last six PADs. I've tried with the GPIO input, all PADs works. The problem was in the GPIO input interrupt example, the code works fine testing one GPIO pin at a time, but I wanted to test multiple pins by setting events with the same function handler in all pins. Doing that, the first and second PADs works fine, but it fails at the third PAD.
Here is the transcript in Questasim:
PHP Code:
run 13ms # [CORE] Core settings: PULP_SECURE = 1, N_PMP_ENTRIES = 16, N_PMP_CFG 4 # [TB] 0ns - Entry point is set to 0x1c008080 # [TB] 0ns - Asserting hard reset # ** Warning: (vsim-3533) [FOFIW] - Failed to open file "fs/file_0_0.txt" for writing. # No such file or directory. (errno = ENOENT) : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_fs_handler.sv(269) # Time: 0 ps Iteration: 0 Instance: /tb_pulp/i_fs_handler/FS_PRINTF_CLUSTER # ** Warning: (vsim-3533) [FOFIW] - Failed to open file "fs/file_31_0.txt" for writing. # No such file or directory. (errno = ENOENT) : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_fs_handler.sv(269) # Time: 0 ps Iteration: 0 Instance: /tb_pulp/i_fs_handler/FS_PRINTF_FC # [TB] 1ns - Using FLL # [TB] 1ns - Not using CAM SDVT # Loading default stimuli # [JTAG] SoftReset Done( 701ns) # [JTAG] Bypass Test Passed ( 33301ns) # [JTAG] Tap ID: 249511c3 ( 43701ns) # [JTAG] Tap ID Test PASSED ( 43701ns) # [test_mode_if] 50301ns - Init # [TB] 50301ns - Enabling clock out via jtag # [test_mode_if] 51801ns - Setting confreg to value 002. # [TB] 51801ns - jtag_conf_reg set to 002 # [TB] 51801ns - Releasing hard reset # [TB] 53401ns - Init PULP TAP # [pulp_tap_if] WRITE32 burst @1c008080 for 4 bytes. # [TB] 67501ns - Write32 PULP TAP # [JTAG] R/W test of L2 succeeded # [TB] 177701ns - Halting the Core # [TB] 236501ns - Writing the boot address into dpc # [TB] 280601ns - Loading L2 via JTAG # [JTAG] Loading L2 with pulp tap jtag interface # [pulp_tap_if] WRITE32 burst @1c000000 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c000400 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c000800 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c000c00 for 840 bytes. # [pulp_tap_if] WRITE32 burst @1c008000 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c008400 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c008800 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c008c00 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c009000 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c009400 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c009800 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c009c00 for 1024 bytes. # [pulp_tap_if] WRITE32 burst @1c00a000 for 832 bytes. # [pulp_tap_if] WRITE32 burst @1c010000 for 240 bytes. # [TB] 10977201ns - Resuming the CORE # [TB] 11550701ns retrying debug reg access # [TB] 11580001ns retrying debug reg access # [TB] 11609301ns retrying debug reg access # [TB] 11638601ns retrying debug reg access # [TB] 11667901ns retrying debug reg access # [TB] 11697201ns retrying debug reg access # [TB] 11726501ns retrying debug reg access # [TB] 11755801ns retrying debug reg access # [TB] 11799801ns - Waiting for end of computation force -freeze pad_spim_sdio0 1 0, 0 20us run 1ms # [STDOUT-CL31_PE0] Got edge. force -freeze pad_spim_sdio1 1 0, 0 20us run 1ms # [STDOUT-CL31_PE0] Got edge. force -freeze pad_spim_sdio2 1 0, 0 20us run 1ms # 15001366ns: Illegal instruction (core 0) at PC 0x00000000: # [STDOUT-CL31_PE0] [ [35mRT(31,0) [0m] [33mWARNING [0m: Reached illegal instruction (PC: 0x0, opcode: 0x0 # [TB] 15302201ns - Received status core: 0x7fffffff # ** Note: $stop : /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_pulp.sv(857) # Time: 15302201 ns Iteration: 0 Instance: /tb_pulp # Break at /home/ivan.hirata/cadence_wd/616/tsmc18_miniasic17_wd/pulpissimo-caninos/sim/../rtl/tb/tb_pulp.sv line 857
And here is the c code of the test:
Code:
/*
* This example shows how to block the core until a GPIO
* value has changed.
*/
// Testing one GPIO PAD
/*
int main()
{
if (rt_event_alloc(NULL, 1)) return -1;
// GPIO initialization
rt_gpio_init(0, GPIO);
rt_pad_set_function(GPIO, 1); //pad_func=1 means gpio functionality. pad_func=0 is default
// Configure GPIO as an inpout
rt_gpio_set_dir(0, 1<<GPIO, RT_GPIO_IS_IN);
// Trigger notifications on both rising and falling edges
rt_gpio_set_sensitivity(0, GPIO, RT_GPIO_SENSITIVITY_EDGE);
// Set the event for the GPIO.
// Note that we use an IRQ event instead of a normal one so that
// the callback is called directly from the IRQ handler.
rt_gpio_set_event(0, GPIO, rt_event_irq_get(gpio_handler, (void *)GPIO));
// Now wait for a few edges and see how long it takes
unsigned long long start = rt_time_get_us();
while(edges < NB_EDGE)
{
rt_event_yield(NULL);
}
unsigned long long end = rt_time_get_us();
printf("Got %d edges in %d us\n", NB_EDGE, end - start);
return 0;
}*/
// Testing all GPIO PADs
int main()
{
if (rt_event_alloc(NULL, 1)) return -1;
// GPIO initialization
for (int i=0; i<32; i++)
{
rt_gpio_init(0, i);
rt_pad_set_function(i, 1); //pad_func=1 means gpio functionality. pad_func=0 is default
}
// Configure GPIO as an inpout
rt_gpio_set_dir(0, 0xffffffff, RT_GPIO_IS_IN);
// Trigger notifications on both rising and falling edges
for (int i=0; i<32; i++)
{
rt_gpio_set_sensitivity(0, i, RT_GPIO_SENSITIVITY_RISE);
}
// Set the event for the GPIO.
// Note that we use an IRQ event instead of a normal one so that
// the callback is called directly from the IRQ handler.
for (int i=0; i<32; i++)
{
rt_gpio_set_event(0, i, rt_event_irq_get(gpio_handler, (void *)i));
while(edges == 0)
{
rt_event_yield(NULL);
}
rt_gpio_set_event(0, i, NULL);
edges = 0;
}
return 0;
}
The only thing I did before "run 13ms" is forcing all PADs to 0. And I verified that the problem is not in the pad_spim_sdio2, I tried starting with GPIO 2 then it failed at GPIO 4.
I am working on implementing of PULPino on FPGA Artix-7 100t and I can I've been able to run some small programs about GPIO and UART etc. But now i am trying to find out a way to read the memory value as well as the register files. According to the datasheet, il tells me that i could use SPI slave to do this, but there is not any more description about it. Then i turn to the testbench in the folder /tb and try to figure out the protocol of SPI Slave. For example, I try to send the 8bits cmd 0x0B, then 32bits address 0x1A110404 and finally try to receive the value in register x1, but there is noting back. I also try to read the system verilog code about the SPI slave, but i could not find somting special.
So has anyone used SPI slave successfully? Or has there some other ways to read the specific memory value and register files?
Hi all,
I guess the current FLL model in PULP setup is not synthesizable. I want to make my own ASIC and looking for open source FLL IPs.
Has anyone used such an IP?
Also wanted to check on my understanding that FLL in its current form is not synthesizable.
A docker container for the RISC-V GNU compiler toolchain has been contributed to this forum. There exists already a Docker container with all the Snitch tools (source and container). A Docker container lowers the entry hurdle, streamlines development on different host environments and allows for CI of projects using PULP infrastructure.
We could merge the efforts into a single Docker container including (but not limited to):
GCC and LLVM toolchains for both PULP and Snitch systems
Simulators such as GVSOC (PULP) and banshee (Snitch)
Verilated models of PULP systems (such as the Snitch-cluster) for cycle-accurate simulations
Please add suggestions for components that should be added to this unified container.
