Hello everyone,

Im currently doing a research for a future proyect about RISC V based core IPs,  chips, devboards fully designed and manufactured in Europe that are being commercialized right now. Preferable if the devboard counts with multiple communication protocols, no FPGAs, less 25W consumption, no SoC.
If in development I  would also appreciate the information. I know SiFive is selling european designed and manufactured RISC V dev boards, but, the RISC V chips themselfs are manufactured in China.

Thank you in advance for the assistance.

Hi, I am Jay Huang, a Verification Engineer at Taiwan Electronic System Design Automation (TESDA). Currently, we are utilizing your open-source SOC, PULPino, to develop our verification tools.

During the course of our SOC implementation, we have encountered some challenges related to the PULPino Boot ROM, prompting us to seek clarification on certain aspects. According to the datasheet Memory Map, the Boot ROM's address range is specified as 0x0008_0000 to 0x0008_0200.

In an attempt to integrate this information into our testbench, I observed that when attempting to read from this address range, no data was retrieved. After further investigation, it was determined that the Boot ROM is, in fact, located immediately following the Instruction Memory, rather than at the specified address.

I would like to ask if it is correct to set the start address of the Boot ROM at 0x0000_8000 if the Instruction Memory is configured as 32KB?
If this configuration is indeed correct, I am curious as to why the Boot ROM's address in the datasheet is documented as 0x0008_0000 to 0x0008_0200.

Your insights and guidance on this matter would be immensely valuable to us in resolving the issues we are currently facing. Thank you for your time and attention to this inquiry.

Hi, 

I was trying to implement a solution to add AES and maybe other crypto extensions in Pulpissimo. I tried to change the core to a variant of the RI5CY, CV32E40S that support some of that extensions. 
When I run a test that worked on the original core, the JTAG halts the core in the simulation. 

I was wondering if there is something to do with the SDK (by the way, i'm using this platform for a while so i'm still using releases 7.0 and pulp-sdk) or the toolchain to make it work, or is it just a problem in the connection of the core. There are quite a few more ports so, just to start trying, I left some of the ports that seemed optional from the documentation. 

Thanks in advance.

Hello,

I am trying to generate pulpino's bitstream without using the processing system loading the programs via SPI SLAVE. I modified the pulpemu folder deleting all the processing system's part and I managed to generate the bitstream but I am getting this warnings:

WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0__0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__1 input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mac input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mul input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/p_0_out input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__0__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/__1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mac output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/mult_i/short_mul output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_pulpino/pulpino_i/core_region_i/CORE.RISCV_CORE/ex_stage_i/p_0_out output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (ZPS7-1) PS7 block required - The PS7 cell must be used in this Zynq design in order to enable correct default configuration.

Then with Vivado I transfer the bitstream to the zedboard and send the code to load the program via SPI SLAVE but I don't get any answer from MISO and it doesn't load the program.

Any help?

One question I have is whether I can deploy pulp with vivado for windows

tôi đang thực hiện SoC dự án Pulissimo trên FPGA. Tôi sử dụng Zedboard. Tôi đã gặp lỗi khi cố gắng sử dụng openocd để conig jtag để gỡ lỗi. Hãy làm theo hướng dẫn trong readme https://github.com/pulp-platform/pulpiss...nd-openocd
Tôi git sao chép và thực thi các lệnh sau xây dựng
bản sao openocd $git https://github.com/pulp-platform/riscv-openocd
$ ./bootstrap
$ ./config --enable-ftdi
$ ./make
$ ./make cài đặt

sau đó tôi sử dụng lệnh để kết nối riscv lõi với máy chủ
$ openocd -f openocd-zedboard-ftdi2232.cfg
Tôi nhận được mã lỗi sau:
Mở Trình gỡ lỗi trên chip 0.10.0+dev-00830-ga88cc98a0 (24-10-10-2023) 16:32)
Được cấp phép theo GNU GPL v2
Đối với các báo cáo lỗi, hãy đọc
http://openocd.org/doc/doxygen/bugs.html
Thông tin: Nghe trên cổng 6666 cho kết nối tcl
Thông tin: Nghe trên cổng 4444 cho kết nối telnet
Thông tin: tốc độ xung nhịp 1000 kHz
Cảnh báo: Không có thao tác nhấn nào được kích hoạt. TỰ ĐỘNG THĂM DÒ CÓ THỂ KHÔNG HOẠT ĐỘNG!!
Lỗi: Việc thẩm vấn chuỗi quét JTAG không thành công: tất cả đều là lỗi
Lỗi: Kiểm tra giao diện JTAG, thời gian, công suất mục tiêu, v.v.
Lỗi: Vẫn cố gắng sử dụng chuỗi quét đã định cấu hình...
Cảnh báo: Bỏ qua các sự kiện thiết lập JTAG do lỗi
Cảnh báo: dịch vụ gdb cần xác định một hoặc nhiều mục tiêu


Sau đó tôi chuyển sang một FPGA khác. cụ thể là kintex kc705. Tôi lại nhận được lỗi sau:
Mở Trình gỡ lỗi trên chip 0.10.0+dev-00830-ga88cc98a0 (2023-10-24-16:32)
Được cấp phép theo GNU GPL v2
Đối với các báo cáo lỗi, hãy đọc
http://openocd.org/doc/doxygen/bugs.html
openocd-kc705.cfg:21: Lỗi: tên lệnh không hợp lệ "ftdi"
trong thủ tục 'script'
tại tệp "embeddedtartup.tcl", dòng 26
tại tệp "openocd-kc705.cfg", dòng 21


Cách định cấu hình bột giấy gỡ lỗi openocd khi được triển khai trên FPGA. Và tôi muốn triển khai Pulissimo xuống Kintex 7 KC705 FPGA. Tôi có thể làm được không? tôi đang gặp rắc rối

I am running a project with pulp-freertos and all the related tools needed to make it run (sdk and riscv toolchain). I am personalizing the 'blink' demo project already present in the github dir project, but I need to debug it. Now the question is...how can I debug it?
Thanks in advance

Hello i'm using Pulpino's SPI Master part to read a external sensor  that it is connected to one of the zedboard's pmod. I have configurated the spi_master_clkgen spi_clk polarity to start in 1. I have done the next code to read the sensor's id but I don't get any success:

#include <utils.h>
#include <stdio.h>
#include <spi.h>
#include <bench.h>
int main() {
    
  int sensor_id; 
    
    spi_setup_master(1);
  *(volatile int*) (SPI_REG_CLKDIV) = 0x2;

    spi_setup_cmd_addr( 0x0f, 8,0,0); 
    spi_set_datalen(8);
    spi_start_transaction(SPI_CMD_RD, SPI_CSN0);
    spi_read_fifo(&sensor_id, 8);
    printf(" LPS25HB sensor id: 0x%x\n", sensor_id);
    return 0;
}

Reviewing the signal with a logic a analizer I got this result: SCLK does as many clocks that spi_Reg_clkdiv value is, the chip select when CS is asserted, it remains asserted indefinitely. MOSI only does one pulse and MISO remains idle.

Anyone can help?

I'm trying to build the HERO project, and I am on the step where I am meant to run " ../test/gen_slm_files.sh <app_name>."
However, I have an issue with line 11 of the file, which is 

Hello,

I am trying to compile the mm-small example in https://github.com/pulp-platform/hero/tr...s/mm-small. I would like to build it only for the PULP accelerator.
For that I run make only=pulp. I get the following error:

herov2/pulp/sdk/pkg/sdk/dev/install/include/archi/pulp.h:31:10: fatal error: 'archi/chips/PULP_CHIP_STR/pulp.h' file not found

Please could you help me identify the source of the problem.

Thank you!