Hi, 

Earlier I used SDK V1 to compile C codes to run over FPGAs, however, I used it with an older version of the RTL. Many changes have been made to the RTL and a new SDK version has been released. 

However, the new SDK doesn't have instructions on how to compile applications for FPGA targets neither I see the same directory structure as the old one.

When I used the V1 SDK to compile the application to run over the Nexys A7 using the new RTL, I faced this issue: 

Quote:19 #include <stdio.h>

20 #include <rt/rt_apt.h>

22 int __rt_fpga_fc_frequency = 10008000; // e.g. 10000800 for 10MHZ;
23 int __rt_fpga_periph_frequency = 5000000; // e.g. 5000000 for SMHZ;
24
(gdb) list

26 int main()

27 {

28 while (1) {

29 printf("Hello World!\n\r");

30 for (volatile int i=6; 1<1000008; i++);

31 }

2 return 0;

(gdb) continue

Continuing.

^c

Program received signal SIGINT, Interrupt.
0x1c009452 in __rt_exit_debug_bridge (status= -1)  at libs/i0/10.c:560
 __rt_bridge_clear_notif();

Hello forum,

I want to ask if there is any way to debug the C code that is running on the pulp-runtime. The solutions that I find (pulp-debug-bridge, openocd and gdb)  works with pulp-sdk and as far I know the sdk is no longer working. Thank you for helping.

Hi,

I want to connect a camera to Pulpissimo's Camera Interface (CPI) on Genesys2 board.  However, most CPI pads are connected to LEDs/buttons/switches on Genesys2 board.  Can I modify the constraints file to remap and connect the CPI signals to the FMC connector so that I can use Digilent FMC Pcam Adapter to connect camera modules?  Any considerations I need to take ?

Thanks,

tparng

Hi, 

I have been trying to program Nexys A7 with the latest Pulpissimo RTL and I am encountering these issues, any clue? 

1. REPORT DETAILS
   

Hello,

I am very interested in using the HERO platform for research, especially on its hrv variant and the VCU128 implementation that is mentioned in the Readme file of the Github repository. It says that it is "under development", but the repository has not had any updates in the last months. Is it still being developed? Is there any other place to look at that I may have missed?

Any kind of guidance or help to advance in that direction would also be greatly appreciated, because it does not seem to be an easy task without some prior knowledge of the platform. I have tried to start from an older port on the Genesys 2 but there seem to be some missing parts.

Thank you in advance. BR,

Pedro Lobo.

I started working with Pulpissimo and I saw that the SDK is not supported any more.
Currently, I was working with the simple runtime and the runtime examples but there are only 3 of them.
Is there any way I could get more examples, dma, timers, gpio ...?  
Is there a way to build the old pulpissimo sdk (branch v1) vene if it is not supported anymore?

Hello,

I would like to deploy the pulp-platform in an Artix fpga but I don't know what files to include in the design and simulation, as well.
Are there any tree file which explains how the files are connected on RTL and Simulation level so that know which is the top level ?

Hello,

getting acquainted with PULP platform these last few weeks - so, first of all, a big thank you and a bigger congratulations to all the creators and contributors.

I haven't had prior experience with tools such gvsoc, so I am bit troubled by trying to wrap my head around where are its limits, actually - hence this post. Please, any clarifications in this discussion would be of great help.

First of all, I've seen the videos from pulp training:

1. Understanding and working with PULP
   
2. GVSoC / Dory Tutorial
   
3. A Deep Dive into HW/SW Development with PULP
   

Hello,

I get this error while I am trying to build the RTL.

How to perform regression test when the compiler is replaced with LLVM, The compiler used by the existing regression test is GCC. I want to compile it with clang to run the regression test. Or, there are other test sets to test whether the clang compiler can correctly generate the instruction of pulp.