Hi,
I am trying to transmit a 32 bit data from memory to UART through Udma. The problem I am facing is udma transmit bus carry only 1byte data. The code I had written to load 32 bit data to memory is:

Hi
Currently I am writing a test bench for transferring a 32 bit data from one location to another memory location in RISCV  pulp. I am bit confused how to set the address of DMA transmit bus and the procedure for transferring the data. Can you help me regarding this

code I wrote for transferring data without DMA is

li x15,64
LUI x14, 0x1c000 // Source address selected is 0x1c000001
sw x15, 001(x14)
LUI x13, 0x1c010  // destination address is 0x1c01000
sw x14, 0(x13)

Hi,

I'm currently starting a project based on Pulpissimo with an Ibex core as Fabric Controller. I got everything set up as described in the Readme. The RTL simulation works fine and I got a (working) implementation running on a Nexys A7 board (ported from the Nexys Video implementation) which I want to use to test some peripherals.
I connect to the board by using a Digilent HS2 JTAG debugger with OpenOCD from the pulp-SDK.

At this point I have a few questions (and problems) regarding the runtime/PulpOS.

There are currently three repositories providing SW support for Pulp/Pulpissimo. The pulp-builder, pulp-sdk, and the pulp-runtime.

I understand that the pulp-runtime is currently a simplified version of the runtime. But as i noticed it seems to have different way of configuring/building.
A) As it is a newer runtime, do you plan to extend this further to replace the "old sdk" at some point?
B) Currently the pulp-runtime supports only the riscy core. Would it be possible to support the ibex as well?

The simple runtime worked on the FPGA out of the box with the riscy core. That was nice  

In the readme of the pulpissimo the pulp-builder is the suggested package to use the runtime and therefor is the same as an SDK, right? But what is the pulp-SDK then?
The runtime and api files seems to be similar. But I encountered different problems with both when using the examples.

E.g. the hello uart example:
With the pulp-builder SDK the Code doesn't even reach the main() part but hangs somewhere during the boot/configuration part.
With the pulp-sdk i can use the UART with printf but not using the UART driver. Also only after using this fix.

C) Now I'm not quite sure which one to use. For which should I use my time to investigate my problems?

Also the SDK seems to use deprecated drivers for the examples (at least the name of the folder is like that). So..
D) Is there any documentation of the runtime and its APIs except for the auto generated docs and the examples in the SDK?
The pulp-builder has an empty Doc folder.

E) Regarding a comment on this issue the support of the SDK regarding the ibex core is not really complete. It seems like nothing has changed much since then.
Are you planing to keep the support for the ibex core?

I hope someone finds the time to answer my questions and I'm looking forward to work with the pulp platform.

Hello,

as you know PULPissimo has an option to boot from flash by setting the LOAD_L2 parameter in the tb_pulp.sv to STANDALONE.
As far as I know it won't actually boot from flash but instead load the data from flash to the L2 and execute it. Is this still the case?

So I was running the hello example from the pulp_rt_examples using the STANDALONE variant.
This works just fine but I was wondering about the contents of the different memories after the end of the computation.

We can see that when using STANDALONE the flash memory uses its preload feature to contain "slm_files/flash_stim.slm" which should be the image of the hello example.
When instead using JTAG there is a different image loaded into L2 called stim.txt.

There are several question which I hope someone can answer:

Hello,

I'm new to using the PULP environment and currently I am trying to familiarize myself with the HERO platform implemented on my ZC706 board and I have a few questions:

• I saw that with OpenMP the workload to execute is sent to the cluster with 8 RISC-V cores.
However, can I choose precisely which cores will be used to run a workload ?
For example, I would like the workload W1 to be executed by cores PE0, PE1 and PE2 and the workload W2 to be executed by cores PE M to PE N-1.

• I suppose it is possible with the ZC706 FPGA board to have 2 clusters of 4 RISC-V cores.
Similar to the previous question, can I choose which cluster will run a workload ?

• I saw in the file "fe/rtl/includes/pulp_soc_defines.sv" on Github that it is possible to define an FPU. But I can't find the apu_package.sv file mentioned in the comment on line 45 to add an FPU.
Is it possible to add an FPU in big-pulp?
Is the FPU shared between the cores or is it one FPU per core ?

• Last question, Is it possible to add a HWCE to a cluster ?


Thanks in advance

Hi,

I have build the PULP RISC-V GNU Compiler Toolchain [1] with multilib. It contains the following targets:

• march=rv32ic, mreg=16:
  This is used for Micro-riscy. What is the difference compared to march=rv32ec of RISC-V GNU Compiler Toolchain [3]?
  
• march=rv32imfcxpulpv2:
  Is this rv32imfc plus the extra instructions introduced in RI5CY? (e.g. hw loops)
  
• march=rv32imcxpulpslim:
  What is this? I saw it has been used for zero-riscy [4]. What is the difference to rv32imc or rv32emc?
  

How are ARA open source going?



Best Regard,
Roy

I'm trying to simulate standalone booting from flash using the bootsel=0 and the bootrom.
What are the steps to prepare an image starting from the compiled elf file?
Do I just need to load it as is in the flash model for simulation, or are there some additional steps required?

Is there some documentation regarding this topic?

Thanks !

Hi,

I'm trying certain software debug tool on pulpissimo. To build alignment between source code and disassembly, I need to trace both "pc" and the corresponding "instruction" in the design during runtime.
I've found the "pc" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.pc_id_i[31:0]"
And probably the "inst" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.instr[31:0]"

For example, on "hello" case, a piece of disassembly is:
   

The waveform is like:
   

you can see when the instruction is 32bit, disassembly is matched with waveform (eg. pc=0x1c008130, inst=0x82f72a23)
But when the instruction is 16bit, looks like I can find a signal in waveform to show the 16bit instruction correctly... for example, pc=0x1c008134, disassembly shows the instruction val=0xc69c; but the 32bit "inst" signal shows different value in the waveform...
Instead, I find the 16bit inst at output of L2 ram... But I can't use the output of L2 ram in my tool since it's too hard to align with pc...

any ideas?

Thank you!

Hello,

Right now I am trying to run the accelerator example on the zedboard, but right now I have a issue regarding of running the application. For some reason after this line of code __rt_periph_wait_event(ARCHI_SOC_EVENT_FCHWPE0, 1), the application loops. What can be a good approach to fix it?