Hi,
I am trying to build the pulp RTL simulaltion platform following the instructions provided on the github page:
https://github.com/pulp-platform/pulp.

At the steps:

Hey All, 

I am trying to integrate NVDLA accelerator into PULPissimo platform through AXI4 interface. Has anyone done it before ? What's the limitations in terms of both hardware and software integration ? 

Thanks !

Hi,

we are using the ri5cy core, pulpinov1 branch, and wanted to understand which spike (isa simulator) repository should be taken.

i have found this:
https://github.com/pulp-platform/riscv-isa-sim
1. is there a specific branch matching the pulpinov1 design version
2. does it have any specific ri5cy compliance, special flags or any other?
3. am i supposed to take any patch to make it match ri5scy, as the toolchain?

for the toolchain, we are taking this :
https://github.com/pulp-platform/ri5cy_gnu_toolchain
which i understand patches the original pulp platform toolchain to match the ri5cy.

would appreciate any help on this topic.

thanks,
Itay K.

Hi,

In Pulpissimo in l2_ram_multi_bank.sv there is hooks for xilinx memories:
`ifdef PULP_FPGA_EMUL

      logic [NB_BANKS-1:0][7:0]   wea;

      genvar                      i,j;
      generate
         for(i=0; i<NB_BANKS; i++)
         begin : CUTS
            for(j=0; j<8; j++)
            assign wea[i][j] = ~mem_slave[i].csn & ~mem_slave[i].wen & mem_slave[i].be[j];

            xilinx_l2_mem_8192x64 l2_mem_i (
               .clka  ( clk_i                                ),
               .rsta  ( ~rst_ni                              ),
               .ena   ( ~mem_slave[i].csn                    ),
               .wea   ( wea[i]                               ),
               .addra ( mem_slave[i].add[MEM_ADDR_WIDTH-1:0] ),
               .dina  ( mem_slave[i].wdata                   ),
               .douta ( mem_slave[i].rdata                   )
            );
         end
      endgenerate

Have you tested this is working?

Regards, skor

Hi, we are developing a RISC-V project which need to add some ISRs for peripheral hardware, is there any tutorial or example to reference??

thanks!!

Hi!

I would like to use eu_evt_maskWaitAndClr() HAL function to put the RISC-V core to sleep until my HWPE signals an event (job done). I am using HERO-SDK.
I tried including eu_v3.h header in my code (between #pragma omp declare target and #pragma omp end declare target), but compiler gives me fatal error: eu_v3.h: No such file or directory. Is it even posible to use headers from pulp-sdk inside hero-sdk project?

Best regards,
Tomislav

Hi,
  I want to try to simluate the bootloader with flash S25fs256s,  so that I can simluate with the  flash. I have found the verilog model of S25fs256s according to https://github.com/pulp-platform/pulpiss.../spi_flash, and I have instantiated the generic pad for each signal coming from my SPI model according to https://github.com/pulp-platform/pulpino/issues/16, and in order to test boot_code, I changed MEMLOAD on https://github.com/pulp-platform/pulpino/blob/master/vsim/tcl_files/run.tcl, from PRELOAD to STANDALONE.  I instantiated the flash module in the pulpion_top file, but when I run "make testSPIMASTER.vsim" or "make helloworld.vsim" ,  but still encounter the error  "RX string: ERROR: Spansion SPI flash not found” ，can someone tell me how to deal with the error? How can make it to find the Spanison SPI flash ?

Hi,

I got following error when synthesising (dc_shell L2016-03) Pulpissimo:


Information: Building the design 'pulp_soc' instantiated from design 'soc_domain_0_1_32_64_32_6_4_6_8_4_8_8' with
        the parameters "CORE_TYPE=0,USE_FPU=1,AXI_ADDR_WIDTH=32,AXI_DATA_IN_WIDTH=64,AXI_DATA_OUT_WIDTH=32,AXI_ID_IN_WIDTH=6,AXI_ID_OUT_WIDTH=4,AXI_USER_WIDTH=6,EVNT_WIDTH=8,BUFFER_WIDTH=8". (HDL-193)
Error:  ../pulpissimo/ips/pulp_soc/rtl/pulp_soc/pulp_soc.sv:269: Syntax error at or near token 'FC_Core_MHARTID': arrays do not have named members. (VER-294)
*** Presto compilation terminated with 2 errors. ***

MikkeN

Hello,

I'm currently porting the Ariane core to the KC705 board, as it is using the same FPGA as the Genesys II this should be a feasible task to do. So far I adapted the constraint file to match the KC705 board and also changed the part and board variables in the Makefile. The KC705 has different amounts of switches and LEDs so I reduced the number where necessary. Also the cpu_reset is inverted on the KC705. In the fpga/scripts/write_cfgmem.tcl I changed the SPI memory size parameter to 128 (as provided by the KC705).
The KC705 doesn't have an FTDI chip like the Genesys II. Therefore, the KC705 lacks the necessary configurable JTAG pins that are connected to the dmi_jtag module. For now I temporarily worked around that by wiring it up to a BSCANE2 module and hardwiring the trst to 1. In the future I plan on using a second JTAG that I connect to some GPIO pins to wire them up to the module.
I also built the ariane-sdk using the provided makefile and put it on an SD card.

The bitstream is sent to the KC705 just fine. I added some additional logic to to make sure the clock and reset are working by wiring them up to the LEDs, so this part seems to be just fine.

I checked the bootrom and according to the main.c in fpga/src/bootrom/src/ it is supposed to 'print_uart("Hello World!\r\n");' in the beginning of the bootrom. However, I don't receive this output (or any other) on my terminal.
I'm using the `screen /dev/ttyUSB0 115200` command from the github readme. I made sure to use the correct ttyUSB by dis- and reconnecting the separate UART cable on the KC705 while checking the /dev folder.

Are there any additional files/settings I need to adjust? Any idea how to get this to work or how to debug it?

Also:     During the `make fpga` an ariane.xpr vivado project file is created in the fpga folder. If I open this file it is empty, is this supposed to be the case? I wanted to add some ILA cores to further debug my issue, but without a working project this gets more tedious.
    
Thank you.

Edit: typos

Hi, 

I have reviewed Pulpissimo code. There is couple of issues (I try to synthesize it):

1. In pulp_soc.sv (line 861) is instatiation of module jtag_tap_top. However this module is not found. Instead there is module tap_top,
should it be instantiated?

2. In soc_clk_rst_gen.sv there is three instatiations of gf22_FLL
Comment says that it is not supported by FPGA
Is this really synthesizable code?
There is comments regarding that it is behavioral coding.

Best Regards,
MikkeN