Welcome, Guest
You have to register before you can post on our site.

Username
  

Password
  





Search Forums

(Advanced Search)

Forum Statistics
» Members: 511
» Latest member: mmrnkbqfexgs
» Forum threads: 296
» Forum posts: 878

Full Statistics

Latest Threads
How to get more detailed ...
Forum: PULP General questions
Last Post: kgf
06-27-2025, 07:42 AM
» Replies: 6
» Views: 2,695
Which SDK to be used to c...
Forum: PULP General questions
Last Post: Archibald
06-27-2025, 02:12 AM
» Replies: 2
» Views: 3,205
Cheshire with two cores
Forum: PULP General questions
Last Post: tomkathy
06-18-2025, 09:17 AM
» Replies: 5
» Views: 2,065
【新手必讀】Relx電子菸煙彈選購指南與保養技巧
Forum: PULP General questions
Last Post: mmrnkbqfexgs
06-18-2025, 07:51 AM
» Replies: 0
» Views: 90
Understanding HWPE integr...
Forum: PULP General questions
Last Post: sillycorn
06-05-2025, 06:45 AM
» Replies: 0
» Views: 192
missing package in pulp-s...
Forum: PULP General questions
Last Post: Renryant
06-02-2025, 07:55 AM
» Replies: 1
» Views: 559
Role of gapy, list of per...
Forum: PULP General questions
Last Post: yoss
04-25-2025, 01:41 PM
» Replies: 7
» Views: 12,516
Pulp - make build
Forum: PULP General questions
Last Post: tomkathy
04-09-2025, 07:58 AM
» Replies: 4
» Views: 2,230
Unable to compile and run...
Forum: PULP General questions
Last Post: victorgervasio
03-25-2025, 09:30 AM
» Replies: 2
» Views: 1,038
__builtin_pulp
Forum: PULP General questions
Last Post: yoss
02-18-2025, 04:31 PM
» Replies: 0
» Views: 566

 
  some questions about pulpissimo L1 memory
Posted by: jsen_che11 - 11-25-2024, 02:16 PM - Forum: PULP General questions - Replies (3)

Hello, this is my first time working with PULPissimo for my research group’s project, and I’ve encountered some questions during its use:

  1. Why does PULPissimo seem to lack an L1 cache?
  2. If both data and instructions rely on the L2 cache for caching, wouldn’t that lead to potential conflicts?
Additionally, I’ve noticed that other PULP platforms seem to include an L1 cache. Could you explain the reasoning behind this design choice in PULPissimo? If there are any misunderstandings in my interpretation, I’d greatly appreciate it if you could point them out. Thank you very much!

Print this item

  Some questions.
Posted by: sungyong - 11-12-2024, 03:31 PM - Forum: PULP General questions - No Replies

what is meaning of CVA6(Ariane)? i think CVA6 is riscv 6 stage cpu?, and how about ariane?

Print this item

  what is meaning of ARA? (vector processor)
Posted by: sungyong - 11-11-2024, 02:00 AM - Forum: PULP General questions - Replies (2)

i have some simple question of the name of vector processor

what is the meaning of ARA? is it come from CVA6?(Ariane)

Print this item

  librbs.so not found (Pulpissimo)
Posted by: Roogadget - 11-04-2024, 03:01 PM - Forum: PULP General questions - Replies (1)

My team and I have moved back to the version from the pulp-training because we cannot get the newer tools to work.

Now we are faced with another issue.

When we go into the pulpissimo/sim and "make run"

There is an error 1 because it cannot find the librbs.so file.

What is this file? it is missing from the tb/remote_bitbang directory.

We are on Ubuntu 22.

Print this item

  Cheshire with two cores
Posted by: andlo47 - 10-30-2024, 06:26 AM - Forum: PULP General questions - Replies (5)

Hi all,

I'm trying to generate a bit file for Cheshire v0.1.0 with two cores for the Genesys2 board using Vivado 2023.2, but get an error stating that timing constraints are not met.
I can generate the bit file from an earlier commit, f316617, of the Cheshire repo. I did remove the USB support as it would not fit on the FPGA of Genesys2.

I'm quite new to this and would appreciate any help. I'm not sure where to start looking.

Regards,
/Andreas

Print this item

  Fatal error: Broken assembler - hello example
Posted by: Roogadget - 10-28-2024, 10:37 AM - Forum: PULP General questions - Replies (3)

I've just setup my pulpissimo environment and when i run the hello example, I get the following:

This is also a problem for another person I work with:

internal error: can't hash `pv.add.h.div2': exists
Assembler messages:
Fatal error: Broken assembler.  No assembly attempted.
make: *** [/home/x/Documents/code/pulpissimo/sw/pulp-runtime/rules/pulpos/default_rules.mk:257: /home/x/Documents/code/pulpissimo/sw/pulp-runtime/hello/build/test/test.o] Error 1

I tired to switch to the v1 sdk but the error is still there.

Print this item

  Pulp - make build
Posted by: Roogadget - 10-25-2024, 07:33 PM - Forum: PULP General questions - Replies (4)

I'm having trouble with the setup of just pulp, i followed the instructions from the website
but when i run make build, i get the following errors.

make[2]: *** [Makefile:87: librbs.so] Error 1
make[2]: Leaving directory '/home/vboxuser/Documents/pulp/rtl/tb/remote_bitbang'
make[1]: *** [Makefile:18: build-deps] Error 2
make[1]: Leaving directory '/home/vboxuser/Documents/pulp/sim'
make: *** [Makefile:124: build] Error 2



I have questasim, ubuntu 22.04 and installed the packages and compilers are instructed.
I've updated my bashrc with the expected exports too.

Resolved, please ignored. It was just an issue of loading the correct config.

Print this item

  mno pulp hwloop error
Posted by: Roogadget - 10-25-2024, 04:27 PM - Forum: PULP General questions - Replies (6)

I went through the pulpissimo setup and when i run the hello rt test.

It gives me an error saying the following:

riscv32-unknown-elf-gcc error: unrecognized command line option -mno-pulp-hwloop.

I ran the following to setup the compiler.

Code:
./configure --prefix=/opt/riscv --with-arch=rv32imfcxpulpv3 --with-abi=ilp32 --enable-multilib
make

Print this item

  CV32E40P/RI5CY Setup
Posted by: e0960179@u.nus.edu - 10-19-2024, 08:51 AM - Forum: PULP General questions - Replies (1)

I am trying to use the CV32E40P/RI5CY core in a school project and am having a lot of trouble with the setup. This is the first time using an open source core so forgive me if some questions seem silly. 

I added all the RTLs according to the manifest here 
https://github.com/openhwgroup/cv32e40p/...fest.flist

However, when I try to synthesize the module on Xilinx Vivado (2023.2), I do not have enough IO pins. Referring to a paper (https://ieeexplore.ieee.org/document/10420491), I noted that there are more BRAMs in their synthesis so I am trying to wrap the inputs and outputs of the core in BRAMs, which seems like the correct direction. The problem is that my synthesis will optimize away my core module. I don't quite know how the BRAM method works. 

Could anyone share about how they went about wrapping their inputs into BRAMs. For example, do you use 3 separate BRAMs for the instruction memory, Data Memory, and a last BRAM for any outputs that come from the core module? Also, how do you read the instruction memory? I don't see any Program Counter module in the RI5CY code. 

Thank you

Print this item

  How to get more detailed information about spatz
Posted by: YiZhi_W - 10-16-2024, 06:12 AM - Forum: PULP General questions - Replies (6)

Hello! I'm a student studying RVV, and I'm very interested in spatz. I have obtained some materials about spatz, including papers, materials in the github repository, PPT on the official website, etc. however, I found that the documentation provided in the github repository is not comprehensive. The introduction in the papers also has some differences from the current hardware design.
I want to know the hardware design details of spatz and how spatz works with snitch. Could you please provide me with more detailed documentation? It will be very helpful to me. 
Thank you very much!

Print this item