Hello there!

I've been trying to generate the Bitstream of any board supported by you, but specifically, I want to generate for Nexys A7.

While trying this, I have the following error, after executing "$ make nexys rev=nexysA7-50T":

ERROR: [Vivado 12-172] File or Directory '/<my path>/pulpissimo/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci' does not exist
INFO: [Common 17-206] Exiting Vivado at Sun Apr 25 10:19:29 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/<my path>/pulpissimo/fpga/pulpissimo-nexys'
make: *** [Makefile:41: nexys] Error 2


I don't know if any Vivado license is required. I followed the README in GitHub, and after executing ./generate-scripts and ./update-ips, export certain env variables, and so on, there is the same issue. I am able to simulate pulpissimo in RTL simulations but in another computer that has QuestaSim license, and I am trying this bitstream generation in another one(that does not have QuestaSim), don't know if that is the problem. 

I tried other boards and it is the same issue.

Thanks for your answer!


EDIT: I realized that you updated the root GitHub with some changes regarding synthesis using Vivado 2020.2. I could fix the problem mentioned before by git pull command. But now, I got these errors:



Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/head_tail_q[0][free] has multiple drivers: i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_data_ffs[0].head_tail_q_reg[0][free]/Q, and i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_ht_ffs[0].head_tail_q_reg[0][free]/Q.

[...]
INFO: [Project 1-461] DRC finished with 16 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2950.625 ; gain = 64.703 ; free physical = 1185 ; free virtual = 7138
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 2 Warnings, 0 Critical Warnings and 17 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:17 2021...
[Mon Apr 26 11:39:17 2021] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:21 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/home/edgar/Documentos/proyecto_disenno_/pulpissimo/fpga/pulpissimo-genesys2'
make: *** [Makefile:8: genesys2] Error 2

It seems to be something related to this:

always @ (posedge CLK)
y = y + 1;
 
always @ (posedge CLK2)
y = y + 3;

[Reference]https://forums.xilinx.com/t5/Synthesis/ERROR-DRC-MDRV-1-Multiple-Driver-Nets/td-p/1025991

Thanks again!

I'm currently going through the training materials and I can't seem to run the hello world example. I get the following error message.

Quote:# Start time: 16:23:39 on Apr 21,2021
# ** Error: (vsim-3816) Optimized design "vopt_tb" cannot be used by this version of the simulator - it was only compiled for a 32-bit version of vsim
# Error loading design
Error loading design
# End time: 16:23:39 on Apr 21,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

Quote:Model Technology ModelSim SE vsim 10.7d Simulator 2019.02 Feb 15 2019

Hi,
   I am unable to run C code with printf statements using synthesized netlist. I have attached a simulation image of the stdout peripheral bus and FSM of Lint 2 AXI module. I notice that the C code runs successfully when no printf statements are given. 

The C code run when I get this issue is

#include <stdio.h>
int main()
{
  printf("Testing !\n");

  return 0;
}


Any thoughts on this issue?

Attached Files

Thumbnail(s)
   

Hi,
   I am trying to synthesize the pulpissimo, I don't find any documentation or specific script  for post-synthesis simulation but I have done the below steps

1) replaced the generic_memory, generic_rom with technology-related cells
2) synthesized soc_domain as top and have obtained synthesis netlist and its sdf file
3) I have replaced the soc_domain.sv with the synthesis netlist in sim/vcompile/rtl/pulpissimo.mk <-- all other files are same, not sure which files to keep and which one to remove 
3) I have added the CORE and CLK libs with -L option in sim/tcl_files/run.tcl

The modules gf2_fll , pulp_clock_gating , pulp_clock_mux2 , cluster_clock_gating , cluster_clock_inverter, pulp_clock_inverter are not synthesized, is any one these modules need to be synthesized for post-synthesis simulation?

what libraries should i need to keep in ./sim/tcl_files/config/vsim_ips.tcl ?

It will be great if someone can help me here

Vignajeth

I just took my first step in scientific research focused on Xilinx ZC706 Evaluation Boards. Recently I find your PULP website 
https://pulp-platform.org/hero/doc/downloads/images/zc706/ . I appreciate your sharing these files here, but when I downloaded them to SD card and started the development board, I found that you did not publish the system login account and password of this example image files.

So could you please send me the login and password of the image files in the website?Or send a new boot image for zc706? I would be sincerely appreciated if you could help .
Thank you very much!

Hi, I have some problems with the synthesis of Pulpissimo to ZedBoard target.

ERROR -> "an enum variable may only be assigned to same enum typed variable or one of its values [pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]"

I previously ran ./update-ips and and the ./generate-scripts. I'm running a webpack licensed 2020.2 version under Linux (Ubuntu 18.04). Do you know where is the problem? 

I attach the complete log file "vivado.txt"

Attached Files

  vivado.txt (Size: 42.54 KB / Downloads: 1)

I notice that Pulp seems to ship with a 2015 version of COIN's CLP/CBC tools. Anyone have a good link showing how to update the COIN tools that ship with Pulp? I'm mostly on Win10.

Is there a way to simultaneously start all timer units in apb advanced timer in pulpissimo?

Hi,

I would like to know if anyone tried to synthesize the Pulpissimo SoC on a PYNQ-Z1 (Zynq-7000) board. The chip is almost the same that is in the zedboard (XC7Z020-1CLG400C) so I though that it would be relatively easy. If so, I would like to know what parameters or files I have to change or rewrite to achieve the compatibility, or how to proceed.  As you can see, I am a beginner on this project, Do you know where to start?

Thank you.

Hi,
    I want to use the IBEX core with pulpissimo. I was able to run Hello World example with default ri5cy core. I changed the following files by making CORE_TYPE as 1 to get the ibex core configured.

• ./pulpissimo/rtl/pulpissimo/pulpissimo.sv
  
• ./pulpissimo/rtl/pulpissimo/soc_domain.sv
  
• ./pulpissimo/rtl/tb/tb_pulp.sv
  
• ./pulpissimo/pulp_soc/rtl/fc/fc_subsystem.sv
  
• ./pulpissimo/ips/pulp_soc/rtl/pulp_soc/pulp_soc.sv
  
• ./pulpissimo/install/tb_pulp.sv