I ran the cv32e40p (RI5CY) core with FPU (floating point) enabled and tried to check the result for all the floating-point operations. I have faced the following issues in case of division and fused operations.
Rounding mode output is incorrect for division, rounding mode for the division is not the same as addition, subtraction, and multiplication
For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
Exception status flags output is incorrect for division, exception status flags output for the division is not the same as addition, subtraction, and multiplication, and doesn't follow IEEE754
For example, the overflow flag is not generated even if the division result generated is infinity (for MAX/MIN case).
Rounding mode output is incorrect for fused operations, rounding mode for fused operations is not the same as addition, subtraction, and multiplication
For example, when rounding mode is RTZ (round to zero), the guard, round and sticky flags aren't ignored and the final output is changed by 1 bit.
Getting output as X in fused operations if any of the operands is 0
For example, If any of the 3 operands are 0 in FMA, the result generated by the core is X.
These are the inputs I have given. All the following data is for 32-bit FPU, input1, input2, input3, output, and the expected output are represented in {1-bit sign, 8-bit exponent, 23-bit mantissa}, and status and expected status are represented as {Invalid, Divide by Zero, Overflow, Underflow, Inexact}
Division:
Input1 - 1_10000010_11011100000100010010000
Input2 - 1_00000001_11110010110000000000000
Out - 0_11111111_00000000000000000000000
Expected out - 0_11111110_11111111111111111111111
Status - 00100
Expected status - 00001
Rounding mode - RTZ (Round to Zero)
Operation - Division
The Input1 is being divided with Inp2 which is a very large number, the result should overflow and give infinity as the output, but as the rounding mode is RTZ (round to zero), the output should be the maximum possible number in a 32-bit floating-point number instead of infinity.
Input1 - 0_00000000_00000000000000000000000
Input2 - 1_11111111_00000000000000000000000
Out - 1_00000000_00000000000000000000000
Expected out - 1_00000000_00000000000000000000000
Status - 00100
Expected status - 00000
Rounding mode - RTZ (Round to Zero)
Operation - Division
0/Inf is giving overflow status even though the output is not infinity
Input1 - 0_01111110_11100000000000000000000
Input2 - 0_01111111_00000000000000000000001
Out - 0_01111110_01111111111111111111111
Expected out - 0_01111110_01111111111111111111110
Status - 00001
Expected status - 00001
Rounding mode - RDN (Round Down)
Operation - Division
The expected data is 0_01111110_01111111111111111111110 but getting output as 0_01111110_01111111111111111111111, both the inputs are positive and the rounding mode is round down, so the output shouldn't be changing because of the rounding mode
Fused Multiply Add:
Input1 - 0_00000000_00000000000000000000000
Input2 - 0_00000000_00000000000000000000000
Input3 - 0_00100100_00101010011010100100100
Out - x_xxxxxxxx_xxxxxxxxxxxxxxxxxxxxxxx
Expected out - 0_00100100_00101010011010100100100
Status - 000xx
Expected status - 00000
As input1 and input2 are 0, the output should be input3, but getting X from the core whenever any one of the inputs is 0 for fused operations.
Please let me know if these are the bugs in the core or the FPU, or if there's anything wrong with my understanding of floating-point operations.
Hi,
I notice in a lot of places in the entire pulpisismo code that contains ifndef depending upon the flag SYNTHESIS, I also notice ASIC_SYNTHESIS flag being used inside the Ri5cy.
I also find PULP_TRAINING flag in the code
I am very new to JTAG and have worked with pulpissimo by running test cases mostly via the Linux terminal, which has Questasimulation.
I wanted to ask that how can I either create or locate an existing stimulifile, and further use it for JTAG programming? Also, which software would be good for JTAG programming?
Usually, when I make and run C-based test cases in the terminal, I am checking whether basic functions are working or not (since we are dealing with a constrained system and also my background is not very strong when it comes to architecture design-based projects). So if I run a test.c file using makefile, when using the command 'make clean all run' does this automatically create a stimulifile for this test.c somewhere in the directory? If yes, how can I locate it?
Hi,
I am working on various things related to GCC, e.g., LTO, GCC plugins etc. on Pulpissimo. To that end I have modified the contents of pulp-gcc-toolchain and pulp-sdk in the past. One thing that caused some problems was the linker option -nostdlib that's inserted by default by pulp-sdk to the generated makefiles. I always expected it to be absolutely necessary and did not scrutinize it further. However, when I simply tried to remove it everything still seems to remain working when running the binary in the FPGA.
So my question is... What's the rationale to use -nostdlib at all? It is included since the very last commit of pulp-sdk.
NB: The sdk also emits -nostartfiles too (which is implied by -nostdlib).
I've been trying to generate the Bitstream of any board supported by you, but specifically, I want to generate for Nexys A7.
While trying this, I have the following error, after executing "$ make nexys rev=nexysA7-50T":
ERROR: [Vivado 12-172] File or Directory '/<my path>/pulpissimo/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci' does not exist
INFO: [Common 17-206] Exiting Vivado at Sun Apr 25 10:19:29 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/<my path>/pulpissimo/fpga/pulpissimo-nexys'
make: *** [Makefile:41: nexys] Error 2
I don't know if any Vivado license is required. I followed the README in GitHub, and after executing ./generate-scripts and ./update-ips, export certain env variables, and so on, there is the same issue. I am able to simulate pulpissimo in RTL simulations but in another computer that has QuestaSim license, and I am trying this bitstream generation in another one(that does not have QuestaSim), don't know if that is the problem.
I tried other boards and it is the same issue.
Thanks for your answer!
EDIT: I realized that you updated the root GitHub with some changes regarding synthesis using Vivado 2020.2. I could fix the problem mentioned before by git pull command. But now, I got these errors:
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/head_tail_q[0][free] has multiple drivers: i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_data_ffs[0].head_tail_q_reg[0][free]/Q, and i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_ht_ffs[0].head_tail_q_reg[0][free]/Q.
[...]
INFO: [Project 1-461] DRC finished with 16 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2950.625 ; gain = 64.703 ; free physical = 1185 ; free virtual = 7138
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 2 Warnings, 0 Critical Warnings and 17 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:17 2021...
[Mon Apr 26 11:39:17 2021] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:21 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/home/edgar/Documentos/proyecto_disenno_/pulpissimo/fpga/pulpissimo-genesys2'
make: *** [Makefile:8: genesys2] Error 2
It seems to be something related to this:
always @ (posedge CLK) y = y + 1; always @ (posedge CLK2)
y = y + 3;
I'm currently going through the training materials and I can't seem to run the hello world example. I get the following error message.
Quote:# Start time: 16:23:39 on Apr 21,2021
# ** Error: (vsim-3816) Optimized design "vopt_tb" cannot be used by this version of the simulator - it was only compiled for a 32-bit version of vsim
# Error loading design
Error loading design
# End time: 16:23:39 on Apr 21,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
I tried modifying the command to use vsim -32 instead of vsim -64 But that made things much worse and gave more errors. So I've reverted it back to normal. My vsim version is as follows.
Quote:Model Technology ModelSim SE vsim 10.7d Simulator 2019.02 Feb 15 2019
Is this supported with Pulp? or should I be trying to run this on a different Sim?
Hi,
I am unable to run C code with printf statements using synthesized netlist. I have attached a simulation image of the stdout peripheral bus and FSM of Lint 2 AXI module. I notice that the C code runs successfully when no printf statements are given.
The C code run when I get this issue is
#include <stdio.h>
int main()
{
printf("Testing !\n");
Hi,
I am trying to synthesize the pulpissimo, I don't find any documentation or specific script for post-synthesis simulation but I have done the below steps
1) replaced the generic_memory, generic_rom with technology-related cells
2) synthesized soc_domain as top and have obtained synthesis netlist and its sdf file
3) I have replaced the soc_domain.sv with the synthesis netlist in sim/vcompile/rtl/pulpissimo.mk <-- all other files are same, not sure which files to keep and which one to remove
3) I have added the CORE and CLK libs with -L option in sim/tcl_files/run.tcl
The modules gf2_fll , pulp_clock_gating , pulp_clock_mux2 , cluster_clock_gating , cluster_clock_inverter, pulp_clock_inverter are not synthesized, is any one these modules need to be synthesized for post-synthesis simulation?
what libraries should i need to keep in ./sim/tcl_files/config/vsim_ips.tcl ?
I just took my first step in scientific research focused on Xilinx ZC706 Evaluation Boards. Recently I find your PULP website https://pulp-platform.org/hero/doc/downloads/images/zc706/ . I appreciate your sharing these files here, but when I downloaded them to SD card and started the development board, I found that you did not publish the system login account and password of this example image files.
So could you please send me the login and password of the image files in the website?Or send a new boot image for zc706? I would be sincerely appreciated if you could help . Thank you very much!
Hi, I have some problems with the synthesis of Pulpissimo to ZedBoard target.
ERROR -> "an enum variable may only be assigned to same enum typed variable or one of its values [pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]"
I previously ran ./update-ips and and the ./generate-scripts. I'm running a webpack licensed 2020.2 version under Linux (Ubuntu 18.04). Do you know where is the problem?
I attach the complete log file "vivado.txt"
Code:
Starting synth_design
Using part: xc7z020clg484-1
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_private_ram/ip/xilinx_private_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
Top: xilinx_pulpissimo
INFO: [Device 21-403] Loading part xc7z020clg484-1
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_merge with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_merge.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:32]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_mux2 [/home/diego/Documents/tfm/pulpissimo/ips/tech_cells_generic/src/deprecated/pulp_clk_cells_xilinx.sv:53]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_gating [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/pulp_clock_gating_xilinx.sv:11]
ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 7 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
INFO: [Common 17-206] Exiting Vivado at Tue Mar 23 19:31:02 2021...
Makefile:11: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard'
Makefile:52: recipe for target 'zedboard' failed
make: *** [zedboard] Error 2
