i have some simple question of the name of vector processor

what is the meaning of ARA? is it come from CVA6?(Ariane)

My team and I have moved back to the version from the pulp-training because we cannot get the newer tools to work.

Now we are faced with another issue.

When we go into the pulpissimo/sim and "make run"

There is an error 1 because it cannot find the librbs.so file.

What is this file? it is missing from the tb/remote_bitbang directory.

We are on Ubuntu 22.

Hi all,

I'm trying to generate a bit file for Cheshire v0.1.0 with two cores for the Genesys2 board using Vivado 2023.2, but get an error stating that timing constraints are not met.
I can generate the bit file from an earlier commit, f316617, of the Cheshire repo. I did remove the USB support as it would not fit on the FPGA of Genesys2.

I'm quite new to this and would appreciate any help. I'm not sure where to start looking.

Regards,
/Andreas

I've just setup my pulpissimo environment and when i run the hello example, I get the following:

This is also a problem for another person I work with:

internal error: can't hash `pv.add.h.div2': exists
Assembler messages:
Fatal error: Broken assembler.  No assembly attempted.
make: *** [/home/x/Documents/code/pulpissimo/sw/pulp-runtime/rules/pulpos/default_rules.mk:257: /home/x/Documents/code/pulpissimo/sw/pulp-runtime/hello/build/test/test.o] Error 1

I tired to switch to the v1 sdk but the error is still there.

I'm having trouble with the setup of just pulp, i followed the instructions from the website
but when i run make build, i get the following errors.

make[2]: *** [Makefile:87: librbs.so] Error 1
make[2]: Leaving directory '/home/vboxuser/Documents/pulp/rtl/tb/remote_bitbang'
make[1]: *** [Makefile:18: build-deps] Error 2
make[1]: Leaving directory '/home/vboxuser/Documents/pulp/sim'
make: *** [Makefile:124: build] Error 2



I have questasim, ubuntu 22.04 and installed the packages and compilers are instructed.
I've updated my bashrc with the expected exports too.

Resolved, please ignored. It was just an issue of loading the correct config.

I went through the pulpissimo setup and when i run the hello rt test.

It gives me an error saying the following:

riscv32-unknown-elf-gcc error: unrecognized command line option -mno-pulp-hwloop.

I ran the following to setup the compiler.

I am trying to use the CV32E40P/RI5CY core in a school project and am having a lot of trouble with the setup. This is the first time using an open source core so forgive me if some questions seem silly. 

I added all the RTLs according to the manifest here 
https://github.com/openhwgroup/cv32e40p/...fest.flist

However, when I try to synthesize the module on Xilinx Vivado (2023.2), I do not have enough IO pins. Referring to a paper (https://ieeexplore.ieee.org/document/10420491), I noted that there are more BRAMs in their synthesis so I am trying to wrap the inputs and outputs of the core in BRAMs, which seems like the correct direction. The problem is that my synthesis will optimize away my core module. I don't quite know how the BRAM method works. 

Could anyone share about how they went about wrapping their inputs into BRAMs. For example, do you use 3 separate BRAMs for the instruction memory, Data Memory, and a last BRAM for any outputs that come from the core module? Also, how do you read the instruction memory? I don't see any Program Counter module in the RI5CY code. 

Thank you

Hello! I'm a student studying RVV, and I'm very interested in spatz. I have obtained some materials about spatz, including papers, materials in the github repository, PPT on the official website, etc. however, I found that the documentation provided in the github repository is not comprehensive. The introduction in the papers also has some differences from the current hardware design.
I want to know the hardware design details of spatz and how spatz works with snitch. Could you please provide me with more detailed documentation? It will be very helpful to me. 
Thank you very much!

Hello! I'm a student using pulp to do some research. I  formerly used the [pulpino] and this platform uses the [RI5CY] core. Now I'm using the [pulpissimo] and it uses the [CV32E40P] core.

I wonder if there is any difference between these two cores. because I found it says "32 bit 4-stage core CV32E40P (formerly RI5CY)", is this means that the difference between them is just name? Because I also compare the CV32E40P's github page and the RI5CY core cloned by the pulpino, there are many difference between files. For example, there is no [tracer] moudle in the [CV32E40P].

Since I want write the core ([RI5CY] or [CV32E40p]) to the FPGA and use it as a controller to control a NPU, I wonder is there a huge difference between these two cores in the PPA(performance, power, area)

Since I'm not a native English speaker, it may cause difficult when you reading my question, I'm very sorry about that!

Thank you very much!

Respected Moderator 


I am currently working on synthesizing the ARA architecture along with the CVA6 processor. I have been trying to perform top-down mapping of the files by designating ara_soc.sv as the top module and consolidating all related files into a single .sv file for synthesis.

Unfortunately, I have encountered difficulties in achieving a successful synthesis in Cadence Genus. I am concerned that my approach might be flawed, and I am seeking guidance on how to resolve this issue.

Could you please provide me with some advice or best practices for synthesizing the ARA and CVA6 design in Cadence Genus or any other tool like Vivado or Synopsis DC? Any insights or suggestions on how to effectively manage the integration of these components would be greatly appreciated.