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Memset in the disassembly...
Forum: PULP General questions
Last Post: RiscV
09-14-2020, 07:02 AM
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Error while building SDK
Forum: PULP General questions
Last Post: Victor
09-12-2020, 01:22 PM
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[Pulpissimo]where are the...
Forum: PULP General questions
Last Post: meggiman
08-29-2020, 02:04 PM
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Some questions about the ...
Forum: PULP General questions
Last Post: akurth
08-27-2020, 01:35 PM
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Offloading APIs available...
Forum: PULP General questions
Last Post: akurth
08-27-2020, 01:30 PM
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Compiling and running app...
Forum: PULP General questions
Last Post: LPLA
08-27-2020, 11:54 AM
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Access Stack Pointer in R...
Forum: PULP General questions
Last Post: RiscV
08-25-2020, 11:01 AM
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Simple RISC-V Assembly In...
Forum: PULP General questions
Last Post: ufsahu
08-21-2020, 05:46 AM
» Replies: 2
» Views: 324
Error while updating IPs
Forum: PULP General questions
Last Post: LPLA
08-20-2020, 11:43 AM
» Replies: 2
» Views: 309
Error while running hello...
Forum: PULP General questions
Last Post: Tresa Febina Francis
08-12-2020, 05:06 PM
» Replies: 0
» Views: 240

  32bit data memory write & read
Posted by: RiscV - 07-03-2020, 09:53 AM - Forum: PULP General questions - No Replies

I am trying to transmit a 32 bit data from memory to UART through Udma. The problem I am facing is udma transmit bus carry only 1byte data. The code I had written to load 32 bit data to memory is:

//loading data to memory
lui x16,0x12345
addi x16,x16,0x678   // 32 bit value- 12345678
lui x14, 0x1c010     // address location 1c01000
sw x16,x14
In the udma_tx_ bus the data found is 78787878 in the address location 1c01000.
I checked the memory banks separately. 78 is copying in all four banks, memory write is not happening at that time.What should I do to transmit the entire 32 bit data to 1c01000 location. I want 12345678 data in 1c01000. Please help me.

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  udma memory to memory data transfer test bench
Posted by: RiscV - 06-29-2020, 09:52 AM - Forum: PULP General questions - Replies (2)

Currently I am writing a test bench for transferring a 32 bit data from one location to another memory location in RISCV  pulp. I am bit confused how to set the address of DMA transmit bus and the procedure for transferring the data. Can you help me regarding this

code I wrote for transferring data without DMA is

li x15,64
LUI x14, 0x1c000 // Source address selected is 0x1c000001
sw x15, 001(x14)
LUI x13, 0x1c010  // destination address is 0x1c01000
sw x14, 0(x13)

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  Questions regarding Runtime/SDK
Posted by: heavySea - 06-22-2020, 01:54 PM - Forum: PULP General questions - Replies (2)


I'm currently starting a project based on Pulpissimo with an Ibex core as Fabric Controller. I got everything set up as described in the Readme. The RTL simulation works fine and I got a (working) implementation running on a Nexys A7 board (ported from the Nexys Video implementation) which I want to use to test some peripherals.
I connect to the board by using a Digilent HS2 JTAG debugger with OpenOCD from the pulp-SDK.

At this point I have a few questions (and problems) regarding the runtime/PulpOS.

There are currently three repositories providing SW support for Pulp/Pulpissimo. The pulp-builder, pulp-sdk, and the pulp-runtime.

I understand that the pulp-runtime is currently a simplified version of the runtime. But as i noticed it seems to have different way of configuring/building.
A) As it is a newer runtime, do you plan to extend this further to replace the "old sdk" at some point?
B) Currently the pulp-runtime supports only the riscy core. Would it be possible to support the ibex as well?

The simple runtime worked on the FPGA out of the box with the riscy core. That was nice Smile 

In the readme of the pulpissimo the pulp-builder is the suggested package to use the runtime and therefor is the same as an SDK, right? But what is the pulp-SDK then?
The runtime and api files seems to be similar. But I encountered different problems with both when using the examples.

E.g. the hello uart example:
With the pulp-builder SDK the Code doesn't even reach the main() part but hangs somewhere during the boot/configuration part.
With the pulp-sdk i can use the UART with printf but not using the UART driver. Also only after using this fix.

C) Now I'm not quite sure which one to use. For which should I use my time to investigate my problems?

Also the SDK seems to use deprecated drivers for the examples (at least the name of the folder is like that). So..
D) Is there any documentation of the runtime and its APIs except for the auto generated docs and the examples in the SDK?
The pulp-builder has an empty Doc folder.

E) Regarding a comment on this issue the support of the SDK regarding the ibex core is not really complete. It seems like nothing has changed much since then.
Are you planing to keep the support for the ibex core?

I hope someone finds the time to answer my questions and I'm looking forward to work with the pulp platform. Smile

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  Data relocation when using LOAD_L2=STANDALONE
Posted by: LPLA - 06-09-2020, 02:10 PM - Forum: PULP General questions - Replies (4)


as you know PULPissimo has an option to boot from flash by setting the LOAD_L2 parameter in the tb_pulp.sv to STANDALONE.
As far as I know it won't actually boot from flash but instead load the data from flash to the L2 and execute it. Is this still the case?

So I was running the hello example from the pulp_rt_examples using the STANDALONE variant.
This works just fine but I was wondering about the contents of the different memories after the end of the computation.

We can see that when using STANDALONE the flash memory uses its preload feature to contain "slm_files/flash_stim.slm" which should be the image of the hello example.
When instead using JTAG there is a different image loaded into L2 called stim.txt.

There are several question which I hope someone can answer:

Is there a reason why the actual data from those images is different?
I'm not talking about formatting but rather the actual data itself.
For example:

The first few lines of the .slm file:
@00000000 00
@00000001 70
@00000002 00
@00000003 00
@00000004 04
@00000005 00
@00000006 00
@00000007 00
@00000008 80
@00000009 80
@0000000A 00
@0000000B 1C

The first few lines of the .txt file:

I'm pretty sure that the memory called "boot rom" contains the boot code which is unrelated to the executed (hello example) code. Is this correct?
The code of the hello example should reside somewhere in L2. Now using QuestaSim to check the contents of the different L2 sections I get confused.
There is some data in .../bank_sram_pri0_i/MEM which looks a bit scattered as there are some undefined entries.
The data in .../bank_sram_pri1_i/MEM is more coherent.
Also there is a bit of data in every 0 cut of every CUT X.
By that i mean ...CUTS[X]/RTL_0/bank_i/cut_0/MEM.

What actually resides in pri0, pri1, cut_0?
I found the data of the stim.txt in L2 (in pri0 but not starting at 0x00000000) but not in a coherent way.
Why is this the case even tho I am using STANDALONE instead of JTAG.

In regards to my previous question there is also the boot-code repo which is what I am currently trying to extend.
If I'm not mistaken the boot_code.cde which I linked to in the above post is the binary of the boot_code.c found in this repo, is that correct?
Looking at the linker script link.ld we can see that there are only two entries in the memory table: ROM and L2.
How is data actually relocated from flash to L2? As far as I remember the flash is not memory mapped or is it?
I'm trying to modify the files in a way which allows me to load (preloaded) data from flash to defined addresses in L2, similar to how the (preloaded) hello example has to somehow be relocated.
Unfortunately I'm not allowed to modify boot_code.c so I'm guessing I have to modify the linker script link.ld and the main startup file crt0.S or add additional files.
Does anyone know if it is actually possible to load data from an arbitrary address in flash to an arbitrary address in L2 during boot phase?

Thank you,

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  Some questions about the HERO platform
Posted by: Olivier - 06-04-2020, 03:38 PM - Forum: PULP General questions - Replies (3)


I'm new to using the PULP environment and currently I am trying to familiarize myself with the HERO platform implemented on my ZC706 board and I have a few questions:

• I saw that with OpenMP the workload to execute is sent to the cluster with 8 RISC-V cores.
However, can I choose precisely which cores will be used to run a workload ?
For example, I would like the workload W1 to be executed by cores PE0, PE1 and PE2 and the workload W2 to be executed by cores PE M to PE N-1.

• I suppose it is possible with the ZC706 FPGA board to have 2 clusters of 4 RISC-V cores.
Similar to the previous question, can I choose which cluster will run a workload ?

• I saw in the file "fe/rtl/includes/pulp_soc_defines.sv" on Github that it is possible to define an FPU. But I can't find the apu_package.sv file mentioned in the comment on line 45 to add an FPU.
Is it possible to add an FPU in big-pulp?
Is the FPU shared between the cores or is it one FPU per core ?

• Last question, Is it possible to add a HWCE to a cluster ?

Thanks in advance

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Smile Target options for PULP RISC-V GNU Compiler Toolchain
Posted by: mehrdad - 06-03-2020, 02:35 PM - Forum: PULP General questions - Replies (2)


I have build the PULP RISC-V GNU Compiler Toolchain [1] with multilib. It contains the following targets:

$ riscv32-unknown-elf-gcc --print-multi-lib

Using PULPissimo's pulp-configs for the processor IPs [2] I could get some info about the targets but still, I have few questions about these targets:
  • march=rv32ic, mreg=16:
    This is used for Micro-riscy. What is the difference compared to march=rv32ec of RISC-V GNU Compiler Toolchain [3]?
  • march=rv32imfcxpulpv2:
    Is this rv32imfc plus the extra instructions introduced in RI5CY? (e.g. hw loops)
  • march=rv32imcxpulpslim:
    What is this? I saw it has been used for zero-riscy [4]. What is the difference to rv32imc or rv32emc?
Thanks and kind regards,

[1] https://github.com/pulp-platform/pulp-ri...-toolchain
[2] https://github.com/pulp-platform/pulp-co.../ips/riscv
[3] https://github.com/riscv/riscv-gnu-toolchain
[4] https://github.com/pulp-platform/pulp-tr...8/Makefile

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  The status of Ariane ARA vector processor?
Posted by: roychen - 05-26-2020, 08:42 AM - Forum: PULP General questions - Replies (1)

How are ARA open source going?

Best Regard,

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  Pulpissimo prepare standalone flash image
Posted by: bbr49 - 05-07-2020, 02:31 PM - Forum: PULP General questions - Replies (3)

I'm trying to simulate standalone booting from flash using the bootsel=0 and the bootrom.
What are the steps to prepare an image starting from the compiled elf file?
Do I just need to load it as is in the flash model for simulation, or are there some additional steps required?

Is there some documentation regarding this topic?

Thanks !

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  How to find the signal which represents 16bit instructions in the design?
Posted by: ninipa - 04-26-2020, 01:37 PM - Forum: PULP General questions - Replies (2)


I'm trying certain software debug tool on pulpissimo. To build alignment between source code and disassembly, I need to trace both "pc" and the corresponding "instruction" in the design during runtime.
I've found the "pc" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.pc_id_i[31:0]"
And probably the "inst" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.instr[31:0]"

For example, on "hello" case, a piece of disassembly is:

The waveform is like:

you can see when the instruction is 32bit, disassembly is matched with waveform (eg. pc=0x1c008130, inst=0x82f72a23)
But when the instruction is 16bit, looks like I can find a signal in waveform to show the 16bit instruction correctly... for example, pc=0x1c008134, disassembly shows the instruction val=0xc69c; but the 32bit "inst" signal shows different value in the waveform...
Instead, I find the 16bit inst at output of L2 ram... But I can't use the output of L2 ram in my tool since it's too hard to align with pc...

any ideas?

Thank you!


I just read RISCV manual, looks like these 16bit instructions are RV32C instructions? Then it's decoded into 32bit instruction in the design and the signal "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.instr[31:0]" is the decoded one, right?
So my question becomes --- can you point me the signal which cycle aligned with certain "pc" signal and the value is original?

Thank you!

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  Accelerator HWPE Example Loops on ZedBoard
Posted by: acastillo - 04-20-2020, 02:21 PM - Forum: PULP General questions - No Replies


Right now I am trying to run the accelerator example on the zedboard, but right now I have a issue regarding of running the application. For some reason after this line of code __rt_periph_wait_event(ARCHI_SOC_EVENT_FCHWPE0, 1), the application loops. What can be a good approach to fix it?

[Image: 79639808-3dc6cf80-818e-11ea-84ad-879a3098e98e.png]

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