Pulpissimo on FPGA

[skor]

Hello,

I have been trying to Synthesize and implement Pulpissimo on Xilinx FPGA using Vivado . There are problems in the syntesized design although elaborated design seems to be Okay.  Have you synthesised Pulpissimo using VIvado and if yes then did you have to do changes to the RTL?

My synthesis basically is completed succesfully, but when I look at the synthesised schematics I can see that for example zynq_clk_i is not connected anywhere, although it should go to ref_clk_i in soc_domain.

Regards, Sirpa

[fconti]

Hello,

I have been trying to Synthesize and implement Pulpissimo on Xilinx FPGA using Vivado . There are problems in the syntesized design although elaborated design seems to be Okay.  Have you synthesised Pulpissimo using VIvado and if yes then did you have to do changes to the RTL?

My synthesis basically is completed succesfully, but when I look at the synthesised schematics I can see that for example zynq_clk_i is not connected anywhere, although it should go to ref_clk_i in soc_domain.

Regards, Sirpa

Hi skor, at this time we do not provide FPGA synthesis scripts for PULPissimo, but there are people in our group working on this topic. The FPGA-related RTL code might be legacy or out of date as of today (e.g. related to older versions of the design); when we release an FPGA flow which works satisfactorily we will highlight this in the readme.

Roughly speaking, the design must be fully synthesizable in the sense that we have taped out actual ICs based on it in several technologies and with a different set of tool flows.
However, for an FPGA deployment special care must be taken towards
- clocking, which will be performed in an entirely different way from what is done on silicon
- I/O buffers and related constraints
- standard cell latch-based memories (e.g. in the core reg-file) should typically be replaced with flip-flops or with BRAMs
- SRAMs have to be replaced with BRAMs
These points have to be managed by hands at the current time to have a working deployment.