Pulpissimo configuration issues and other bugs

[MikkeN]

Hi,

we have synthesized Pulpissimo with Vivado (2018.3) to FPGA and with Design Compiler (2018) to silicon technology.
Now Pulpissimo code has been changed so, that Design Compiler can't synthesize it anymore.
Vivado synthesize it without issues.

Module LZC gives syntax error from this statement:
assign cnt_o   = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : $clog2(WIDTH)'(0);

Also there is number of bus with conflicts which are quite painful to correct by user.

Can you make code cleaning and check that it passes Design Compiler?
I am also worried about quality of results in FPGA, because Vivado has not seen issues which exist.

[meggiman]

Hi MikkeN,

It is very hard for us to help you without knowing what the actual problem is. I just tried with Synopsys DC 2017.09 and Synopsys DC 2018.06 (we do not have 2018.03). Analysis and elaboration of the LZC module went through without any issues.  Can you provide us the error message? Also, it would help if you provided file path and line numbers in the future. Otherwise, its unnecessary additional work for us to figure out which statement you're referring to.

Greetings,

Manuel

[MikkeN]

Hi MikkeN,

It is very hard for us to help you without knowing what the actual problem is. I just tried with Synopsys DC 2017.09 and Synopsys DC 2018.06 (we do not have 2018.03). Analysis and elaboration of the LZC module went through without any issues.  Can you provide us the error message? Also, it would help if you provided file path and line numbers in the future. Otherwise, its unnecessary additional work for us to figure out which statement you're referring to.

Greetings,

Manuel

Hi Manuel.

lzc issue is actually related to Synopys DC 2016.03. When I use DC 2018.03 there is not error reported. Error message in 2016.03 is:

Error:  ../pulpissimo/ips/common_cells/src/lzc.sv:90: The construct 'constant function call as casting type except with $bits()' is not supported.  (VER-721)
Compiling source file ../pulpissimo/ips/common_cells/src/rstgen_bypass.sv
Error:  Cannot recover from previous errors. (VER-518)

Other issues are existing also with Synopsys DC 2018.03. Those happen in elaboration phase (first one I have debugged and seems that there is real bus width mismatch. Are you using some other than master branch when doing ASIC synthesis? I took Pulpissimo from GIT yesterday and these same errors still exist:

Error: Width mismatch on port 'gpio_in' of reference to 'soc_peripherals' in 'pulp_soc_0_1_1_32_64_32_6_6_6_8_8'. (LINK-3)
Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/soc_peripherals_i ('soc_peripherals') to 'soc_peripherals_17_32_32_8_1_8_43_64_4_2_I_apb_slave_APB_BUS__I_apb_eu_master_APB_BUS__I_apb_hwpe_master_APB_BUS__I_apb_debug_master_APB_BUS__I_l2_rx_master_XBAR_TCDM_BUS__I_l2_tx_master_XBAR_TCDM_BUS__I_soc_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32I_per_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32I_cluster_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32'. (LINK-25)

soc_peripherals.sv
   parameter NGPIO          = 64,                          (line 20)
   input  logic [NGPIO-1:0]           gpio_in,             (line 75)

pulp_soc.sv 
   input  logic [31:0]                   gpio_in_i,        (line 165)

-> gpio_in is 64bit width in soc_peripherals and 32bit width in pulp_soc

Error: Width mismatch on port 'axi_slave_w_data' of reference to 'axi_slice_dc_slave' in 'axi_slice_dc_slave_wrap_32_32_6_6_8_I_axi_slave_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_axi_master_async_AXI_BUS_ASYNC__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_32_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6'. (LINK-3)

Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/dc_fifo_datain_bus_i/axi_slice_i ('axi_slice_dc_slave') to 'axi_slice_dc_slave_32_32_6_6_8'. (LINK-25)


Error: Width mismatch on port 'AXI_Master_w_data_o' of reference to 'soc_interconnect' in 'soc_interconnect_wrap_4_2_4_15_13_6_6_13_32_64_8_6_6_I_lint_fc_data_XBAR_TCDM_BUS__I_lint_fc_instr_XBAR_TCDM_BUS__I_lint_udma_tx_XBAR_TCDM_BUS__I_lint_udma_rx_XBAR_TCDM_BUS__I_lint_debug_XBAR_TCDM_BUS__I_lint_hwpe_XBAR_TCDM_BUS__I_axi_from_cluster_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_axi_to_cluster_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_apb_periph_bus_APB_BUS__I_mem_l2_bus_UNICAD_MEM_BUS_32__I_mem_l2_pri_bus_UNICAD_MEM_BUS_32__I_mem_rom_bus_UNICAD_MEM_BUS_32__'. (LINK-3)

Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect ('soc_interconnect') to 'soc_interconnect_4_4_2_15_13_13_6_6_32_64_8_6_6'. (LINK-25)

[MikkeN]

Hi MikkeN,

It is very hard for us to help you without knowing what the actual problem is. I just tried with Synopsys DC 2017.09 and Synopsys DC 2018.06 (we do not have 2018.03). Analysis and elaboration of the LZC module went through without any issues.  Can you provide us the error message? Also, it would help if you provided file path and line numbers in the future. Otherwise, its unnecessary additional work for us to figure out which statement you're referring to.

Greetings,

Manuel

Hi Manuel.

lzc issue is actually related to Synopys DC 2016.03. When I use DC 2018.03 there is not error reported. Error message in 2016.03 is:

Error:  ../pulpissimo/ips/common_cells/src/lzc.sv:90: The construct 'constant function call as casting type except with $bits()' is not supported.  (VER-721)
Compiling source file ../pulpissimo/ips/common_cells/src/rstgen_bypass.sv
Error:  Cannot recover from previous errors. (VER-518)

Other issues are existing also with Synopsys DC 2018.03. Those happen in elaboration phase (first one I have debugged and seems that there is real bus width mismatch. Are you using some other than master branch when doing ASIC synthesis? I took Pulpissimo from GIT yesterday and these same errors still exist:

Error: Width mismatch on port 'gpio_in' of reference to 'soc_peripherals' in 'pulp_soc_0_1_1_32_64_32_6_6_6_8_8'. (LINK-3)
Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/soc_peripherals_i ('soc_peripherals') to 'soc_peripherals_17_32_32_8_1_8_43_64_4_2_I_apb_slave_APB_BUS__I_apb_eu_master_APB_BUS__I_apb_hwpe_master_APB_BUS__I_apb_debug_master_APB_BUS__I_l2_rx_master_XBAR_TCDM_BUS__I_l2_tx_master_XBAR_TCDM_BUS__I_soc_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32I_per_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32I_cluster_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32'. (LINK-25)

soc_peripherals.sv
   parameter NGPIO          = 64,                          (line 20)
   input  logic [NGPIO-1:0]           gpio_in,             (line 75)

pulp_soc.sv 
   input  logic [31:0]                   gpio_in_i,        (line 165)

-> gpio_in is 64bit width in soc_peripherals and 32bit width in pulp_soc

Error: Width mismatch on port 'axi_slave_w_data' of reference to 'axi_slice_dc_slave' in 'axi_slice_dc_slave_wrap_32_32_6_6_8_I_axi_slave_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_axi_master_async_AXI_BUS_ASYNC__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_32_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6'. (LINK-3)

Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/dc_fifo_datain_bus_i/axi_slice_i ('axi_slice_dc_slave') to 'axi_slice_dc_slave_32_32_6_6_8'. (LINK-25)


Error: Width mismatch on port 'AXI_Master_w_data_o' of reference to 'soc_interconnect' in 'soc_interconnect_wrap_4_2_4_15_13_6_6_13_32_64_8_6_6_I_lint_fc_data_XBAR_TCDM_BUS__I_lint_fc_instr_XBAR_TCDM_BUS__I_lint_udma_tx_XBAR_TCDM_BUS__I_lint_udma_rx_XBAR_TCDM_BUS__I_lint_debug_XBAR_TCDM_BUS__I_lint_hwpe_XBAR_TCDM_BUS__I_axi_from_cluster_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_axi_to_cluster_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_apb_periph_bus_APB_BUS__I_mem_l2_bus_UNICAD_MEM_BUS_32__I_mem_l2_pri_bus_UNICAD_MEM_BUS_32__I_mem_rom_bus_UNICAD_MEM_BUS_32__'. (LINK-3)

Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect ('soc_interconnect') to 'soc_interconnect_4_4_2_15_13_13_6_6_32_64_8_6_6'. (LINK-25)

ANY NEWS? I still see same issues!

[meggiman]

Hi MikkeN,

It is very hard for us to help you without knowing what the actual problem is. I just tried with Synopsys DC 2017.09 and Synopsys DC 2018.06 (we do not have 2018.03). Analysis and elaboration of the LZC module went through without any issues.  Can you provide us the error message? Also, it would help if you provided file path and line numbers in the future. Otherwise, its unnecessary additional work for us to figure out which statement you're referring to.

Greetings,

Manuel

Hi Manuel.

lzc issue is actually related to Synopys DC 2016.03. When I use DC 2018.03 there is not error reported. Error message in 2016.03 is:

Error:  ../pulpissimo/ips/common_cells/src/lzc.sv:90: The construct 'constant function call as casting type except with $bits()' is not supported.  (VER-721)
Compiling source file ../pulpissimo/ips/common_cells/src/rstgen_bypass.sv
Error:  Cannot recover from previous errors. (VER-518)

Other issues are existing also with Synopsys DC 2018.03. Those happen in elaboration phase (first one I have debugged and seems that there is real bus width mismatch. Are you using some other than master branch when doing ASIC synthesis? I took Pulpissimo from GIT yesterday and these same errors still exist:

Error: Width mismatch on port 'gpio_in' of reference to 'soc_peripherals' in 'pulp_soc_0_1_1_32_64_32_6_6_6_8_8'. (LINK-3)
Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/soc_peripherals_i ('soc_peripherals') to 'soc_peripherals_17_32_32_8_1_8_43_64_4_2_I_apb_slave_APB_BUS__I_apb_eu_master_APB_BUS__I_apb_hwpe_master_APB_BUS__I_apb_debug_master_APB_BUS__I_l2_rx_master_XBAR_TCDM_BUS__I_l2_tx_master_XBAR_TCDM_BUS__I_soc_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32I_per_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32I_cluster_fll_master_FLL_BUS__FLL_ADDR_WIDTH_32_FLL_DATA_WIDTH_32'. (LINK-25)

soc_peripherals.sv
   parameter NGPIO          = 64,                          (line 20)
   input  logic [NGPIO-1:0]           gpio_in,             (line 75)

pulp_soc.sv 
   input  logic [31:0]                   gpio_in_i,        (line 165)

-> gpio_in is 64bit width in soc_peripherals and 32bit width in pulp_soc

Error: Width mismatch on port 'axi_slave_w_data' of reference to 'axi_slice_dc_slave' in 'axi_slice_dc_slave_wrap_32_32_6_6_8_I_axi_slave_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_axi_master_async_AXI_BUS_ASYNC__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_32_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6'. (LINK-3)

Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/dc_fifo_datain_bus_i/axi_slice_i ('axi_slice_dc_slave') to 'axi_slice_dc_slave_32_32_6_6_8'. (LINK-25)


Error: Width mismatch on port 'AXI_Master_w_data_o' of reference to 'soc_interconnect' in 'soc_interconnect_wrap_4_2_4_15_13_6_6_13_32_64_8_6_6_I_lint_fc_data_XBAR_TCDM_BUS__I_lint_fc_instr_XBAR_TCDM_BUS__I_lint_udma_tx_XBAR_TCDM_BUS__I_lint_udma_rx_XBAR_TCDM_BUS__I_lint_debug_XBAR_TCDM_BUS__I_lint_hwpe_XBAR_TCDM_BUS__I_axi_from_cluster_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_axi_to_cluster_AXI_BUS__AXI_ADDR_WIDTH_32_AXI_DATA_WIDTH_64_AXI_ID_WIDTH_6_AXI_USER_WIDTH_6I_apb_periph_bus_APB_BUS__I_mem_l2_bus_UNICAD_MEM_BUS_32__I_mem_l2_pri_bus_UNICAD_MEM_BUS_32__I_mem_rom_bus_UNICAD_MEM_BUS_32__'. (LINK-3)

Error: Unable to match ports of cell soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect ('soc_interconnect') to 'soc_interconnect_4_4_2_15_13_13_6_6_32_64_8_6_6'. (LINK-25)

ANY NEWS? I still see same issues!

Hi MikkeN

We are aware of these  problems and in the process of fixing them. What we normally do when taping out a chip that contains pulpissimo is using a custom tailored toplevel module on a different server (due to confidential technology files) since each chip contains a different configuration (e.g. nr of gpios, additional accelerators or memory bank configuration). Of course it would be desirable to have the pulpissimo toplevel synthesizable as is and we are in the process of applying the necessary fixes. We hope to arrive there in the next couple of months but right now we do not have the capacity to give this task top priority. If it's really urgent, I would suggest to fix the port width mismatch issue yourself and we would be extremely thankful if in the end you could contribute your findings as part of a pull-request on Github back to the project.

Greetings,
Manuel